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authorStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-27 14:02:36 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-27 23:48:35 +0200
commit13e4182119bcfcf09bdd9fa2b0cc5d09cd3550c2 (patch)
tree286cfd31710cf8817b1969d4552ea0fa778a66b4 /src/southbridge/amd
parentd0398f135f61c8e9c4d50655d08a35d2816690fb (diff)
downloadcoreboot-13e4182119bcfcf09bdd9fa2b0cc5d09cd3550c2.tar.xz
kbuild: automatically include southbridges
This change switches all southbridge vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in southbridge/Makefile.inc or in southbridge/<vendor>/Makefile.inc. In order to be able to drop southbridge/amd/Makefile.inc, some scattered source files had to be moved to a southbridge/amd/common directory, in accordance to what we are doing on other architectures already. This means, vendor and southbridge directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9796 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/Makefile.inc27
-rw-r--r--src/southbridge/amd/agesa/Makefile.inc1
-rw-r--r--src/southbridge/amd/agesa/hudson/pci.c2
-rw-r--r--src/southbridge/amd/amd8111/Makefile.inc4
-rw-r--r--src/southbridge/amd/amd8131/Makefile.inc4
-rw-r--r--src/southbridge/amd/amd8132/Makefile.inc4
-rw-r--r--src/southbridge/amd/amd8151/Makefile.inc4
-rw-r--r--src/southbridge/amd/cimx/Makefile.inc9
-rw-r--r--src/southbridge/amd/cimx/sb800/late.c2
-rw-r--r--src/southbridge/amd/common/Makefile.inc7
-rw-r--r--src/southbridge/amd/common/amd_pci_util.c (renamed from src/southbridge/amd/amd_pci_util.c)0
-rw-r--r--src/southbridge/amd/common/amd_pci_util.h (renamed from src/southbridge/amd/amd_pci_util.h)0
-rw-r--r--src/southbridge/amd/cs5535/Makefile.inc4
-rw-r--r--src/southbridge/amd/cs5536/Makefile.inc6
-rw-r--r--src/southbridge/amd/pi/hudson/pci.c2
-rw-r--r--src/southbridge/amd/rs690/Makefile.inc4
-rw-r--r--src/southbridge/amd/rs780/Makefile.inc4
-rw-r--r--src/southbridge/amd/sb600/Makefile.inc4
-rw-r--r--src/southbridge/amd/sb700/Makefile.inc4
-rw-r--r--src/southbridge/amd/sb800/Makefile.inc4
-rw-r--r--src/southbridge/amd/sr5650/Makefile.inc4
21 files changed, 67 insertions, 33 deletions
diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
deleted file mode 100644
index cfb89d5a1d..0000000000
--- a/src/southbridge/amd/Makefile.inc
+++ /dev/null
@@ -1,27 +0,0 @@
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8131) += amd8131
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8132) += amd8132
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8151) += amd8151
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS690) += rs690
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB600) += sb600
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS780) += rs780
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB700) += sb700
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB800) += sb800
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SR5650) += sr5650
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += agesa
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += pi
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += pi
-
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c
diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc
index fdd5d8047a..89d41b4a97 100644
--- a/src/southbridge/amd/agesa/Makefile.inc
+++ b/src/southbridge/amd/agesa/Makefile.inc
@@ -16,5 +16,6 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson
diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c
index 5858cd2ef7..cf1626d252 100644
--- a/src/southbridge/amd/agesa/hudson/pci.c
+++ b/src/southbridge/amd/agesa/hudson/pci.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "hudson.h"
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <bootstate.h>
diff --git a/src/southbridge/amd/amd8111/Makefile.inc b/src/southbridge/amd/amd8111/Makefile.inc
index c5b2688e0d..4c9ebaed88 100644
--- a/src/southbridge/amd/amd8111/Makefile.inc
+++ b/src/southbridge/amd/amd8111/Makefile.inc
@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8111),y)
+
ramstage-y += amd8111.c
ramstage-y += usb.c
ramstage-y += lpc.c
@@ -9,3 +11,5 @@ ramstage-y += nic.c
ramstage-y += pci.c
ramstage-y += smbus.c
ramstage-y += reset.c
+
+endif
diff --git a/src/southbridge/amd/amd8131/Makefile.inc b/src/southbridge/amd/amd8131/Makefile.inc
index ce96c9717b..8ec269157c 100644
--- a/src/southbridge/amd/amd8131/Makefile.inc
+++ b/src/southbridge/amd/amd8131/Makefile.inc
@@ -1 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8131),y)
+
ramstage-y += bridge.c
+
+endif
diff --git a/src/southbridge/amd/amd8132/Makefile.inc b/src/southbridge/amd/amd8132/Makefile.inc
index ce96c9717b..75dce39f54 100644
--- a/src/southbridge/amd/amd8132/Makefile.inc
+++ b/src/southbridge/amd/amd8132/Makefile.inc
@@ -1 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y)
+
ramstage-y += bridge.c
+
+endif
diff --git a/src/southbridge/amd/amd8151/Makefile.inc b/src/southbridge/amd/amd8151/Makefile.inc
index dcb3c73543..07edf58085 100644
--- a/src/southbridge/amd/amd8151/Makefile.inc
+++ b/src/southbridge/amd/amd8151/Makefile.inc
@@ -1 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8151),y)
+
ramstage-y += agp3.c
+
+endif
diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc
index aacfc5844b..0754469b4e 100644
--- a/src/southbridge/amd/cimx/Makefile.inc
+++ b/src/southbridge/amd/cimx/Makefile.inc
@@ -16,10 +16,15 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900
-romstage-y += cimx_util.c
+romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c
+romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c
+romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c
-ramstage-y += cimx_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index f4a7aa341a..ffa3290c8c 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -38,7 +38,7 @@
#include "sb_cimx.h" /* AMD CIMX wrapper entries */
#include "smbus.h"
#include "fan.h"
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
/*implement in mainboard.c*/
void set_pcie_reset(void);
diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc
new file mode 100644
index 0000000000..1f847cd0bb
--- /dev/null
+++ b/src/southbridge/amd/common/Makefile.inc
@@ -0,0 +1,7 @@
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c
diff --git a/src/southbridge/amd/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c
index 9f2cc5c1ee..9f2cc5c1ee 100644
--- a/src/southbridge/amd/amd_pci_util.c
+++ b/src/southbridge/amd/common/amd_pci_util.c
diff --git a/src/southbridge/amd/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h
index 1d1e52baaf..1d1e52baaf 100644
--- a/src/southbridge/amd/amd_pci_util.h
+++ b/src/southbridge/amd/common/amd_pci_util.h
diff --git a/src/southbridge/amd/cs5535/Makefile.inc b/src/southbridge/amd/cs5535/Makefile.inc
index 6f65e2e30d..3785cd4002 100644
--- a/src/southbridge/amd/cs5535/Makefile.inc
+++ b/src/southbridge/amd/cs5535/Makefile.inc
@@ -1,4 +1,8 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5535),y)
+
ramstage-y += cs5535.c
#ramstage-y += pci.c
#ramstage-y += ide.c
ramstage-y += chipsetinit.c
+
+endif
diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc
index f36dcc54a6..2da076e14a 100644
--- a/src/southbridge/amd/cs5536/Makefile.inc
+++ b/src/southbridge/amd/cs5536/Makefile.inc
@@ -17,8 +17,12 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
+
ramstage-y += cs5536.c
ramstage-y += ide.c
ramstage-y += pirq.c
ramstage-y += smbus.c
-romstage-y += smbus.c \ No newline at end of file
+romstage-y += smbus.c
+
+endif
diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c
index 70e2c18854..5e71b4b242 100644
--- a/src/southbridge/amd/pi/hudson/pci.c
+++ b/src/southbridge/amd/pi/hudson/pci.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "hudson.h"
-#include <southbridge/amd/amd_pci_util.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <bootstate.h>
static void pci_init(struct device *dev)
diff --git a/src/southbridge/amd/rs690/Makefile.inc b/src/southbridge/amd/rs690/Makefile.inc
index e0cf927812..c80ed9b611 100644
--- a/src/southbridge/amd/rs690/Makefile.inc
+++ b/src/southbridge/amd/rs690/Makefile.inc
@@ -1,5 +1,9 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS690),y)
+
ramstage-y += rs690.c
ramstage-y += cmn.c
ramstage-y += pcie.c
ramstage-y += ht.c
ramstage-y += gfx.c
+
+endif
diff --git a/src/southbridge/amd/rs780/Makefile.inc b/src/southbridge/amd/rs780/Makefile.inc
index bf51d83e8f..1a8a17acac 100644
--- a/src/southbridge/amd/rs780/Makefile.inc
+++ b/src/southbridge/amd/rs780/Makefile.inc
@@ -1,5 +1,9 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS790),y)
+
ramstage-y += rs780.c
ramstage-y += cmn.c
ramstage-y += pcie.c
ramstage-y += ht.c
ramstage-y += gfx.c
+
+endif
diff --git a/src/southbridge/amd/sb600/Makefile.inc b/src/southbridge/amd/sb600/Makefile.inc
index 37fe57df1a..cd5bb6166d 100644
--- a/src/southbridge/amd/sb600/Makefile.inc
+++ b/src/southbridge/amd/sb600/Makefile.inc
@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB600),y)
+
ramstage-y += sb600.c
ramstage-y += usb.c
ramstage-y += lpc.c
@@ -10,3 +12,5 @@ ramstage-y += pci.c
ramstage-y += reset.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
+
+endif
diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc
index 6e772fe5d1..5ec84312a3 100644
--- a/src/southbridge/amd/sb700/Makefile.inc
+++ b/src/southbridge/amd/sb700/Makefile.inc
@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB700),y)
+
ramstage-y += sb700.c
ramstage-y += usb.c
ramstage-y += lpc.c
@@ -15,3 +17,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
romstage-y += early_setup.c
romstage-y += smbus.c
+
+endif
diff --git a/src/southbridge/amd/sb800/Makefile.inc b/src/southbridge/amd/sb800/Makefile.inc
index d665af4639..fca4a984cb 100644
--- a/src/southbridge/amd/sb800/Makefile.inc
+++ b/src/southbridge/amd/sb800/Makefile.inc
@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB800),y)
+
ramstage-y += sb800.c
ramstage-y += usb.c
ramstage-y += lpc.c
@@ -11,3 +13,5 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
ramstage-y += reset.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
+
+endif
diff --git a/src/southbridge/amd/sr5650/Makefile.inc b/src/southbridge/amd/sr5650/Makefile.inc
index 3c17be07c0..f695a112a6 100644
--- a/src/southbridge/amd/sr5650/Makefile.inc
+++ b/src/southbridge/amd/sr5650/Makefile.inc
@@ -1,5 +1,9 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SR5650),y)
+
ramstage-y += sr5650.c
ramstage-y += pcie.c
ramstage-y += ht.c
romstage-y += early_setup.c
+
+endif