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| author | Marc Jones <marc.jones@se-eng.com> | 2012-11-13 15:07:45 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2013-03-09 00:09:37 +0100 |
| commit | e7ae96f48834d57fd1a6c8940fa3f64b97520ed9 (patch) | |
| tree | 34a5d2b6bb7bf08b82b5d1a8bf88c94294c704f7 /src/southbridge/intel/bd82x6x/nvs.h | |
| parent | 4733c647bc64cef86f03efd64a145e4da6fef123 (diff) | |
| download | coreboot-e7ae96f48834d57fd1a6c8940fa3f64b97520ed9.tar.xz | |
Add Intel Panther Point USB3 initialization
Add PEI updates and ACPI updates for supporting EHCI to XHCI
USB port support.
Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2519
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/nvs.h')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/nvs.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index b8506d4db4..7b8b6c9e9c 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -113,7 +113,9 @@ typedef struct { u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; + u8 rsvd11[6]; + /* XHCI */ + u8 xhci; /* IGD OpRegion (not implemented yet) */ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ u8 ibtt; /* 0xb8 - IGD boot type */ |