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authorElyes HAOUAS <ehaouas@noos.fr>2016-07-28 21:20:04 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 18:29:13 +0200
commit1bcd7fcb6199528fc82685e161d6b39f273a1962 (patch)
tree90e07ca28aa8514375b27b9c638a33701f921d52 /src/southbridge/intel/i82371eb
parent15279a9696c70b82c2223264a505da9122f9aa7b (diff)
downloadcoreboot-1bcd7fcb6199528fc82685e161d6b39f273a1962.tar.xz
src/southbridge: Capitalize CPU, RAM and ROM
Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15941 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Diffstat (limited to 'src/southbridge/intel/i82371eb')
-rw-r--r--src/southbridge/intel/i82371eb/fadt.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index 9d0e15c976..b77ed4a292 100644
--- a/src/southbridge/intel/i82371eb/fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
@@ -78,11 +78,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */
fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */
fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */
- fadt->flush_size = 0; /* only needed if cpu wbinvd is broken */
+ fadt->flush_size = 0; /* only needed if CPU wbinvd is broken */
fadt->flush_stride = 0;
fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
fadt->duty_width = 3; /* this width is in bits */
- fadt->day_alrm = 0x0d; /* rtc cmos ram offset */
+ fadt->day_alrm = 0x0d; /* rtc cmos RAM offset */
fadt->mon_alrm = 0x0; /* not supported */
fadt->century = 0x0; /* not supported */
/*