summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82801jx/fadt.c
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-06-21 16:18:27 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-22 08:27:23 +0000
commit27387c3cf5c681b1f52fd45ebe232df593e5d052 (patch)
tree8b499178a28aa3b8a4b07a6659162ab74ccb6c3c /src/southbridge/intel/i82801jx/fadt.c
parent4cdc698707741f4542f8a5757b3c17e66f3dddd9 (diff)
downloadcoreboot-27387c3cf5c681b1f52fd45ebe232df593e5d052.tar.xz
sb/intel/i82801jx: Drop `c3_latency`
The three mainboards using this southbridge do not define it. Note that the default value of zero might be wrong, so add a FIXME comment. Change-Id: Id16bb12a4628daf311bddf7e4701fc480d6b18e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/i82801jx/fadt.c')
-rw-r--r--src/southbridge/intel/i82801jx/fadt.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c
index f2b408b119..d99872d396 100644
--- a/src/southbridge/intel/i82801jx/fadt.c
+++ b/src/southbridge/intel/i82801jx/fadt.c
@@ -36,7 +36,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
fadt->p_lvl2_lat = 1;
- fadt->p_lvl3_lat = chip->c3_latency;
+ fadt->p_lvl3_lat = 0; /* FIXME: Is this correct? */
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;