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authorElyes HAOUAS <ehaouas@noos.fr>2018-09-17 08:44:18 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-18 16:22:03 +0000
commit38f1d13a755548ee8afaf9b5e19d8b6709b9e55d (patch)
treedd9d756059a029174459b55d29dbb0ac0539cdd0 /src/southbridge/intel/lynxpoint/pch.c
parent32ca3cd246746c2a1d584e4a63bcd43ebb7fe23f (diff)
downloadcoreboot-38f1d13a755548ee8afaf9b5e19d8b6709b9e55d.tar.xz
src/{sb/intel,mb/google/auron}: Don't use device_t
Use of device_t is deprecated. Change-Id: I564319506870f75eab58cce535d4e3535a64a993 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.c')
-rw-r--r--src/southbridge/intel/lynxpoint/pch.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index 1a390cca42..cb01de7496 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -80,7 +80,7 @@ u16 get_gpiobase(void)
#ifndef __SMM__
/* Put device in D3Hot Power State */
-static void pch_enable_d3hot(device_t dev)
+static void pch_enable_d3hot(struct device *dev)
{
u32 reg32 = pci_read_config32(dev, PCH_PCS);
reg32 |= PCH_PCS_PS_D3HOT;
@@ -88,7 +88,7 @@ static void pch_enable_d3hot(device_t dev)
}
/* Set bit in Function Disble register to hide this device */
-void pch_disable_devfn(device_t dev)
+void pch_disable_devfn(struct device *dev)
{
switch (dev->path.pci.devfn) {
case PCI_DEVFN(19, 0): /* Audio DSP */
@@ -285,7 +285,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
pch_iobp_write(address, data);
}
-void pch_enable(device_t dev)
+void pch_enable(struct device *dev)
{
u32 reg32;