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authorAngel Pons <th3fanbus@gmail.com>2020-10-30 15:30:48 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-11-03 23:40:48 +0000
commit1b85692fc4247659a188cba577ba8c35aa373fbd (patch)
tree4a7731ad8c64e1d37c23473acd786ed53edb3bc7 /src/southbridge/intel
parent4c2389e28c4fe0c153d3153732d353d5960150f5 (diff)
downloadcoreboot-1b85692fc4247659a188cba577ba8c35aa373fbd.tar.xz
sb/intel/lynxpoint/sata.c: Don't enable Bus Master
Bus Master is not required and reference code does not set it. Tested on Asrock B85M Pro4, still boots from SATA SSD with TianoCore. Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/lynxpoint/sata.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 510440b76a..e1a2fa5a57 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -41,9 +41,8 @@ static void sata_init(struct device *dev)
/* SATA configuration */
- /* Enable BARs */
- pci_write_config16(dev, PCI_COMMAND,
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ /* Enable memory space decoding for ABAR */
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
if (config->ide_legacy_combined) {
printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");