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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-07-30 11:37:14 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-08-07 12:35:33 +0000
commitd1a0c5770803e45dabecf6094fccb9895ea76d10 (patch)
tree8c949297438a11ebdc39d0ea148ef24559917df8 /src/southbridge/intel
parentab1d2ac626d0535191b5f612707ae8f22c46c538 (diff)
downloadcoreboot-d1a0c5770803e45dabecf6094fccb9895ea76d10.tar.xz
usbdebug: Consolidate EHCI_BAR setup
There is assumption of static EHCI_BAR_INDEX, try to clean it up by bringing BAR programming at one spot. Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/common/usb_debug.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index eeac6d92dc..e1cd6575d0 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -63,10 +63,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Bail out. No console to complain in. */
if (!dev)
return;
-
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}