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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-30 04:14:19 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-10-05 13:21:00 +0000
commitad787e18e0ed24495132d0e9e638ed835afad354 (patch)
tree9ee07a78a871830740879127c7c3f14094a57dd1 /src/southbridge
parent81ade745b19194fbad3e3d51d0dac6ca76de1f01 (diff)
downloadcoreboot-ad787e18e0ed24495132d0e9e638ed835afad354.tar.xz
intel/i945,i82801gx: Refactor early PCI bridge reset
Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index d615b403ac..fec891982f 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -39,6 +39,8 @@
void i82801gx_enable(struct device *dev);
#endif
+void ich7_p2p_secondary_reset(void);
+
void enable_smbus(void);
#if ENV_ROMSTAGE