diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2018-06-28 14:13:06 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-30 18:58:22 +0000 |
| commit | 2dc63895eb9250137c216ced33fb63fc91e0402a (patch) | |
| tree | 7341bc0fc41f30c20580329138055b58f5aefc68 /src/southbridge | |
| parent | ecb2399ab878ef0127630e1fd16942a842d92163 (diff) | |
| download | coreboot-2dc63895eb9250137c216ced33fb63fc91e0402a.tar.xz | |
sb/intel/bd82x6x/finalize: Use new PMBASE API
Change-Id: Id42bbea1f2deb0be80af2c8008045d37a926126a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/finalize.c | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index 06010d7192..a08535e979 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -18,16 +18,13 @@ #include <device/pci_ops.h> #include <console/post_codes.h> #include <cpu/x86/smm.h> -#include "pch.h" +#include <southbridge/intel/common/pmbase.h> #include <spi-generic.h> #include "chip.h" #include "pch.h" void intel_pch_finalize_smm(void) { - u16 tco1_cnt; - u16 pmbase; - if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_RO) || IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) { /* Copy flash regions from FREG0-4 to PR0-4 @@ -72,10 +69,7 @@ void intel_pch_finalize_smm(void) pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); /* TCO_Lock */ - pmbase = smm_get_pmbase(); - tco1_cnt = inw(pmbase + TCO1_CNT); - tco1_cnt |= TCO_LOCK; - outw(tco1_cnt, pmbase + TCO1_CNT); + write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK); /* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); |