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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-06-15 12:29:23 +0300 |
|---|---|---|
| committer | Nico Huber <nico.huber@secunet.com> | 2013-06-21 15:51:22 +0200 |
| commit | e761b71e52e699abcfd22cc5e931b89cf354476e (patch) | |
| tree | e785eb4ff54277f5186ae957c5de60b27d203c3f /src/southbridge | |
| parent | cca685936aeadfba65ecbeb854dbe632d6c89e95 (diff) | |
| download | coreboot-e761b71e52e699abcfd22cc5e931b89cf354476e.tar.xz | |
bd82x6x: Fix early EHCI BAR programming
Change EHCI #2 to different BAR from EHCI #1.
Even if the ECHI controllers are not to be addressed, it is bad idea
to set two different devices to claim the same PCI memory cycles.
Change-Id: Ib6f7cfac5acf3f8170508547d1584af90273e8c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3471
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_usb.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index f4e526d85f..baf8c4fed7 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -49,9 +49,9 @@ void enable_usb_bar(void) cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb0, PCI_COMMAND, cmd); - /* USB Controller 1 */ + /* USB Controller 2 */ pci_write_config32(usb1, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); + PCH_EHCI2_TEMP_BAR0); cmd = pci_read_config32(usb1, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb1, PCI_COMMAND, cmd); |