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| author | Marc Jones <marc.jones@amd.com> | 2008-05-06 16:56:47 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2008-05-06 16:56:47 +0000 |
| commit | 9d9518ff54607f8576d45a8664bc9cf88981d6db (patch) | |
| tree | a289636b0f506f7aa418611fd079f56168beb995 /src/southbridge | |
| parent | c314b2fcecda9ce360e5dbb6fdebc51b11554792 (diff) | |
| download | coreboot-9d9518ff54607f8576d45a8664bc9cf88981d6db.tar.xz | |
cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only doing a
pci_write_config8.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/cs5536/cs5536_ide.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536_ide.c b/src/southbridge/amd/cs5536/cs5536_ide.c index c20fada517..b0d711c948 100644 --- a/src/southbridge/amd/cs5536/cs5536_ide.c +++ b/src/southbridge/amd/cs5536/cs5536_ide.c @@ -43,7 +43,7 @@ static void ide_init(struct device *dev) // NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set ide_cfg = pci_read_config32(dev, IDE_CFG); ide_cfg |= CHANEN | PWB; - pci_write_config8(dev, IDE_CFG, ide_cfg); + pci_write_config32(dev, IDE_CFG, ide_cfg); } static void ide_enable(struct device *dev) |