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authorLijian Zhao <lijian.zhao@intel.com>2018-03-26 18:37:16 -0700
committerMartin Roth <martinroth@google.com>2018-04-05 15:59:57 +0000
commit32c3069fd7d076a41ceb5a0453bd9ec1ec9f8559 (patch)
treea925ec06d4b3725d64db7f2271f3e6795c85df50 /src/vendorcode/intel
parent2a50a1f534177965651244557198ee05235f8891 (diff)
downloadcoreboot-32c3069fd7d076a41ceb5a0453bd9ec1ec9f8559.tar.xz
intel/fsp: Update cannonlake fsp header
Fsp revison 7.x.2A.20 also updated MemInfoHob.h to fix SMBIOS Type 17 Offset 15h Speed report incorrectly issue. BUG=None TEST=Boot up with meowth platform and run dmidecode to see two dimm entries under Type 17. Change-Id: Ie1c4df162e75535ad458709452a76de01e31907e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25378 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h
index 941a891bff..99dd815973 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h
@@ -202,6 +202,7 @@ typedef struct {
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+ UINT16 Speed; ///< The maximum capable speed of the device, in MHz.
} DIMM_INFO;
typedef struct {