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authorJett Rink <jettrink@chromium.org>2019-05-15 13:40:05 -0600
committerDuncan Laurie <dlaurie@chromium.org>2019-05-16 15:47:12 +0000
commitce2c1cb742b17623978f3d9a9e414552189bc819 (patch)
tree5a756e83ce13c0d6a0c1ba756e7cd070be94d113 /src
parentf42344a38963cba10604901a6934c7842db42c4d (diff)
downloadcoreboot-ce2c1cb742b17623978f3d9a9e414552189bc819.tar.xz
mb/google/sarien: leave gpio pads unlocks during fsp
The FSP will lock down the configuration of GPP_A12, which makes the configuration of the GPIO pin on warm reset not work correctly. This is only needed for the Arcada variant since it is the only variant that uses ISH. BRANCH=sarien BUG=b:132719369 TEST=ISH_GP6 now works on warm resets on arcarda Change-Id: Icb3bae2c48eee053189f1a878f5975c6afe51c71 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32831 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 27c61f3563..b6377ba55d 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -26,6 +26,7 @@ chip soc/intel/cannonlake
register "PchPmSlpS4MinAssert" = "4" # 4s
register "PchPmSlpSusMinAssert" = "4" # 4s
register "PchPmSlpAMinAssert" = "4" # 2s
+ register "PchUnlockGpioPads" = "1"
register "speed_shift_enable" = "1"
register "psys_pmax" = "140"