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authorAndrey Petrov <andrey.petrov@intel.com>2016-04-08 14:31:54 -0700
committerMartin Roth <martinroth@google.com>2016-04-11 17:56:57 +0200
commit064a50160a55058a7baa00a91cbb9ceb0126cda6 (patch)
tree41c0933eaba8bbc10bee2df7562a1b01656d3712 /src
parent54e055179dd19307a8e8ac2c94b224ebe988ed5d (diff)
downloadcoreboot-064a50160a55058a7baa00a91cbb9ceb0126cda6.tar.xz
cpu/x86/tsc: Compile TSC timer for postcar as well
Change-Id: I8fd79d438756aae03649e320d4d640cee284d88a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14298 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/x86/tsc/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc
index 7e2eab2062..9751cacc87 100644
--- a/src/cpu/x86/tsc/Makefile.inc
+++ b/src/cpu/x86/tsc/Makefile.inc
@@ -2,6 +2,7 @@ bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c
ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
+postcar-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
endif