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authorTeo Boon Tiong <boon.tiong.teo@intel.com>2016-12-28 18:56:26 +0800
committerAaron Durbin <adurbin@chromium.org>2017-01-19 08:50:44 +0100
commitd8e34b2c44605d2eb6ed1a955148ac24b9d0cd2e (patch)
treed559fb2824ad00b29e2dbc04523c6e1cec167860 /src
parent951ec96f17100692daed8c5316ffa13a7ed387d9 (diff)
downloadcoreboot-d8e34b2c44605d2eb6ed1a955148ac24b9d0cd2e.tar.xz
driver/intel/fsp1_1: Fix boot failure for non-verstage case
Currently car_stage_entry is defined only in romstage_after_verstage and as a result when SEPARATE_VERSTAGE is not selected, there is no entry point into romstage and romstage will not be started at all. The solution is move out romstage_after_verstage.S from fsp1.1 driver to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the build and boot issue with this change. Besides that, rename the romstage_after_verstage to romstage_c_entry in more appropriate naming convention after this fix. Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0), romstage can be started successfully. Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/17976 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/drivers/intel/fsp1_1/Makefile.inc1
-rw-r--r--src/drivers/intel/fsp1_1/car.c2
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/car.h2
-rw-r--r--src/soc/intel/skylake/romstage/Makefile.inc1
-rw-r--r--src/soc/intel/skylake/romstage/car_stage.S (renamed from src/drivers/intel/fsp1_1/romstage_after_verstage.S)8
5 files changed, 8 insertions, 6 deletions
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index 4088293e3f..e2f75eee51 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -28,7 +28,6 @@ romstage-y += fsp_util.c
romstage-y += hob.c
romstage-y += raminit.c
romstage-y += romstage.c
-romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
romstage-y += stack.c
romstage-y += stage_cache.c
romstage-$(CONFIG_MMA) += mma_core.c
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 1a5f9a8333..e1a9b9db6c 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -68,7 +68,7 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
}
/* Entry point taken when romstage is called after a separate verstage. */
-asmlinkage void *romstage_after_verstage(void)
+asmlinkage void *romstage_c_entry(void)
{
/* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
* is still enabled. We can directly access work buffer here. */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h
index 88dca9a0c5..5214d73b29 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/car.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/car.h
@@ -32,7 +32,7 @@ struct cache_as_ram_params {
/* Entry points from the cache-as-ram assembly code. */
asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params);
asmlinkage void after_cache_as_ram(void *chipset_context);
-asmlinkage void *romstage_after_verstage(void);
+asmlinkage void *romstage_c_entry(void);
/* Per stage calls from the above two functions. The void * return from
* cache_as_ram_stage_main() is the stack pointer to use in RAM after
* exiting cache-as-ram mode. */
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index c19301f734..47c8c7e39c 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,5 +1,6 @@
verstage-y += power_state.c
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage_fsp20.S
romstage-y += pmc.c
romstage-y += power_state.c
diff --git a/src/drivers/intel/fsp1_1/romstage_after_verstage.S b/src/soc/intel/skylake/romstage/car_stage.S
index 2a3372f905..9482456922 100644
--- a/src/drivers/intel/fsp1_1/romstage_after_verstage.S
+++ b/src/soc/intel/skylake/romstage/car_stage.S
@@ -13,13 +13,15 @@
* GNU General Public License for more details.
*/
-#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
+/* I/O delay between post codes on failure */
+#define LHLT_DELAY 0x50000
.text
.global car_stage_entry
car_stage_entry:
- call romstage_after_verstage
- #include "after_raminit.S"
+ call romstage_c_entry
+ #include "src/drivers/intel/fsp1_1/after_raminit.S"
+
movb $0x69, %ah
jmp .Lhlt