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| author | Sebastian Andrzej Siewior <bigeasy@linutronix.de> | 2012-10-26 19:01:17 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-10-26 21:54:50 +0200 |
| commit | 50dd47bb58bee2ed159c1c5f6eb51dd583094f26 (patch) | |
| tree | f3a93433b5d285edecb51bfe89c789037863bc15 /src | |
| parent | 66fa9e2865dc68fd3d89714138c8e0d27ff16819 (diff) | |
| download | coreboot-50dd47bb58bee2ed159c1c5f6eb51dd583094f26.tar.xz | |
northbridge/sch: Read the GPU memory from the correct PCI device
The GGC register which contains the size of memory that is used for GPU
is in PCI device 2,0 and not 0,0. It is set to to 4MiB in
src/mainboard/iwave/iWRainbowG6/romstage.c.
Change-Id: Ie9f1cc60544ecd9cad770f34c83c33564a6129d4
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-on: http://review.coreboot.org/1628
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sch/northbridge.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index fb3bff8492..4ca1248a0b 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -144,7 +144,7 @@ static void pci_domain_set_resources(device_t dev) tseg_memory_size = tseg_size * 1024ULL; } - reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); + reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(2, 0)), GGC); if (!(reg16 & 2)) { int uma_size = 0; printk(BIOS_DEBUG, "IGD decoded, subtracting "); |