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| author | Bora Guvendik <bora.guvendik@intel.com> | 2020-11-13 21:35:19 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:34:38 +0000 |
| commit | c3c3e453ff4e6d73b52d88ab08a708610997f334 (patch) | |
| tree | b6378e41023baaa508f09b64ed694621f800fda0 /src | |
| parent | f9961fff31b3d91616e3526a4430733270fc109b (diff) | |
| download | coreboot-c3c3e453ff4e6d73b52d88ab08a708610997f334.tar.xz | |
soc/intel/tigerlake: Fix overlapping memory address used for early GSPI2 and UART bars
BAR address used during early initilization of GPSI 2 is overlapping with UART bar.
//For GSPI2 this is the address calculated
GSPI_BUS_BASE(0xFE030000,2)=0xFE032000
GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB)
//overlaps with
CONSOLE_UART_BASE_ADDRESS -> 0xfe032000
Change-Id: Id9f2140a6dd21c2cb8d75823cc83cced0c660179
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index e962e4cccc..b97b92e46d 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -168,7 +168,7 @@ config SOC_INTEL_UART_DEV_MAX config CONSOLE_UART_BASE_ADDRESS hex - default 0xfe032000 + default 0xfe03e000 depends on INTEL_LPSS_UART_FOR_CONSOLE # Clock divider parameters for 115200 baud rate |