diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2019-01-29 01:54:38 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-30 11:17:25 +0000 |
| commit | 19f5201463ff3ffe26754a69df493a37a6c96a05 (patch) | |
| tree | f2cb311716b34be31c886b511f52e2de78b63a9e /src | |
| parent | 9204355b4d2a7dbde41dff262f223a6b7ac674b2 (diff) | |
| download | coreboot-19f5201463ff3ffe26754a69df493a37a6c96a05.tar.xz | |
mainboard/intel/cannonlake_rvp: Enable SaGv config
This patch enables SaGv on Intel CNL-Y and CNL-U RVP board
Change-Id: I8a4b8a2a365caed304935bf0d66db9a92d10c23f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31132
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 9604210794..e5f867cbdc 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -5,7 +5,7 @@ chip soc/intel/cannonlake end # FSP configuration - register "SaGv" = "SaGv_FixedHigh" + register "SaGv" = "SaGv_Enabled" register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index e2ebaba1cb..a6d329be82 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -5,7 +5,7 @@ chip soc/intel/cannonlake end # FSP configuration - register "SaGv" = "SaGv_FixedHigh" + register "SaGv" = "SaGv_Enabled" register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" |