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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-13 10:51:59 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-14 11:30:43 +0000 |
| commit | a1928cfa28e4a589a9f8c1b349edd234c38d87ec (patch) | |
| tree | 182a0885ef31a6773dff7cd593efa2eebbe48d69 /src | |
| parent | 2452afbe04584d48a9d76535f943c0cfc641aa19 (diff) | |
| download | coreboot-a1928cfa28e4a589a9f8c1b349edd234c38d87ec.tar.xz | |
sb/intel/i82801gx: Don't setup CIR when the northbridge is x4x
The northbridge code to set up DMI is not correct and the CIR bits
relate to that.
This fixes a regression caused by 2437fe9 'sb/intel/i82801gx: Move CIR
init to a common place', where payloads hang on southbridge IO.
Change-Id: Iabb54d9954d442a1a7b48a6c6e76faa8079a4c71
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36809
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_init.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 0bd6198e2c..f91a5dc1d0 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -112,6 +112,9 @@ void i82801gx_early_init(void) RCBA8(OIC) = 0x03; RCBA8(OIC); - ich7_setup_cir(); + /* A lot of CIR bits relate DMI setup which is likely not correctly + done for x4x. The issue is also present on ICH10. */ + if (!CONFIG(NORTHBRIDGE_INTEL_X4X)) + ich7_setup_cir(); } #endif |