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| author | FENG yu ning <fengyuning1984@gmail.com> | 2008-12-15 02:32:11 +0000 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2008-12-15 02:32:11 +0000 |
| commit | a8faa2a47935992e4b18ca49cccf921cdbf88e9a (patch) | |
| tree | 6768bb6995339105d4fa23340505d29446853805 /util/flashrom/chipset_enable.c | |
| parent | e65dcfa07a6eb435de302b60adde5ab9ad7ca9cc (diff) | |
| download | coreboot-a8faa2a47935992e4b18ca49cccf921cdbf88e9a.tar.xz | |
* add a generic preop-opcode-pair table.
* rename ich_check_opcodes to ich_init_opcodes.
* let ich_init_opcodes do not need to access flashchip structure:
. move the definition of struct preop_opcode_pair to a better place
. remove preop_opcode_pairs from 'struct flashchip'
. modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure
* call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works.
* fix a coding style mistake.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom/chipset_enable.c')
| -rw-r--r-- | util/flashrom/chipset_enable.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/util/flashrom/chipset_enable.c b/util/flashrom/chipset_enable.c index d2ae21279a..b5af401078 100644 --- a/util/flashrom/chipset_enable.c +++ b/util/flashrom/chipset_enable.c @@ -339,6 +339,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, printf("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + ich_init_opcodes(); break; case BUS_TYPE_ICH9_SPI: tmp2 = *(uint16_t *) (spibar + 0); |