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-rw-r--r--src/mainboard/dell/latitude_e6230/Kconfig63
-rw-r--r--src/mainboard/dell/latitude_e6230/Kconfig.name2
-rw-r--r--src/mainboard/dell/latitude_e6230/Makefile.inc3
-rw-r--r--src/mainboard/dell/latitude_e6230/acpi/ec.asl106
-rw-r--r--src/mainboard/dell/latitude_e6230/acpi/platform.asl12
-rw-r--r--src/mainboard/dell/latitude_e6230/acpi/superio.asl3
-rw-r--r--src/mainboard/dell/latitude_e6230/acpi_tables.c36
-rw-r--r--src/mainboard/dell/latitude_e6230/board_info.txt7
-rw-r--r--src/mainboard/dell/latitude_e6230/devicetree.cb115
-rw-r--r--src/mainboard/dell/latitude_e6230/dsdt.asl32
-rw-r--r--src/mainboard/dell/latitude_e6230/gpio.c208
-rw-r--r--src/mainboard/dell/latitude_e6230/hda_verb.c76
-rw-r--r--src/mainboard/dell/latitude_e6230/mainboard.c28
-rw-r--r--src/mainboard/dell/latitude_e6230/romstage.c63
-rw-r--r--src/mainboard/dell/latitude_e6230/smihandler.c35
15 files changed, 789 insertions, 0 deletions
diff --git a/src/mainboard/dell/latitude_e6230/Kconfig b/src/mainboard/dell/latitude_e6230/Kconfig
new file mode 100644
index 0000000000..486f95ec54
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/Kconfig
@@ -0,0 +1,63 @@
+if BOARD_DELL_LATITUDE_E6230
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_12288
+ select EC_ACPI
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select SUPERIO_SMSC_ECE5048
+ select EC_DELL_MEC5055
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config MAINBOARD_DIR
+ string
+ default dell/latitude_e6230
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Latitude E6230"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0166"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x532
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1028
+
+config DRAM_RESET_GATE_GPIO # FIXME: check this
+ int
+ default 60
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 1
+endif
diff --git a/src/mainboard/dell/latitude_e6230/Kconfig.name b/src/mainboard/dell/latitude_e6230/Kconfig.name
new file mode 100644
index 0000000000..95c821573f
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E6230
+ bool "Latitude E6230"
diff --git a/src/mainboard/dell/latitude_e6230/Makefile.inc b/src/mainboard/dell/latitude_e6230/Makefile.inc
new file mode 100644
index 0000000000..ff95f41428
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/Makefile.inc
@@ -0,0 +1,3 @@
+romstage-y += gpio.c
+bootblock-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/latitude_e6230/acpi/ec.asl b/src/mainboard/dell/latitude_e6230/acpi/ec.asl
new file mode 100644
index 0000000000..95ba5943b9
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/acpi/ec.asl
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (EC0)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 0x10)
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x930, 0x930, 1, 1)
+ IO (Decode16, 0x934, 0x934, 1, 1)
+ })
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ OperationRegion (ECOR, EmbeddedControl, 0, 0xFF)
+ Field (ECOR, ByteAcc, Lock, Preserve)
+ {
+ EC00, 8,
+ EC01, 8,
+ EC02, 8,
+ EC03, 8,
+ EC04, 8,
+ EC05, 8,
+ EC06, 8,
+ EC07, 8,
+ EC08, 8,
+ EC09, 8,
+ EC10, 8,
+ EC11, 8,
+ EC12, 8,
+ EC13, 8,
+ EC14, 8,
+ EC15, 8,
+ EC16, 8,
+ EC17, 8,
+ EC18, 8,
+ EC19, 8,
+ EC20, 8,
+ EC21, 8,
+ EC22, 8,
+ EC23, 8,
+ EC24, 8,
+ EC25, 8,
+ EC26, 8,
+ EC27, 8,
+ EC28, 8,
+ EC29, 8,
+ EC30, 8,
+ EC31, 8,
+ EC32, 8,
+ EC33, 8,
+ EC34, 8,
+ EC35, 8,
+ EC36, 8,
+ EC37, 8,
+ EC38, 8,
+ EC39, 8,
+ EC40, 8,
+ EC41, 8,
+ EC42, 8,
+ EC43, 8,
+ EC44, 8,
+ EC45, 8,
+ EC46, 8,
+ EC47, 8,
+ EC48, 8,
+ EC49, 8
+ }
+
+ Device (BAT0)
+ {
+ Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PCL, Package (0x01) // _PCL: Power Consumer List
+ {
+ _SB
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Method (_BIF, 0, NotSerialized) // _BIF: Battery Information
+ {
+ Name (BIF1, Package (0x0D) {})
+ Return (BIF1)
+ }
+
+ Method (_BST, 0, NotSerialized) // _BST: Battery Status
+ {
+ Name (BST1, Package (0x04) {})
+ Return (BST1)
+ }
+ }
+
+ Method (_Q66, 0, NotSerialized)
+ {
+ Store("EC: _Q66", Debug)
+ Notify (BAT0, 0x81) // Information Change
+ }
+}
diff --git a/src/mainboard/dell/latitude_e6230/acpi/platform.asl b/src/mainboard/dell/latitude_e6230/acpi/platform.asl
new file mode 100644
index 0000000000..0c54ecdf58
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK,1)
+{
+ /* FIXME: EC support */
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/latitude_e6230/acpi/superio.asl b/src/mainboard/dell/latitude_e6230/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/latitude_e6230/acpi_tables.c b/src/mainboard/dell/latitude_e6230/acpi_tables.c
new file mode 100644
index 0000000000..6b731ccfc7
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/acpi_tables.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/latitude_e6230/board_info.txt b/src/mainboard/dell/latitude_e6230/board_info.txt
new file mode 100644
index 0000000000..b63992fbf1
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/board_info.txt
@@ -0,0 +1,7 @@
+Category: laptop
+Board URL: http://www.dell.com/support/home/us/en/19/product-support/product/latitude-e6230
+ROM protocol: SPI
+ROM package: SOIC-8
+ROM socketed: n
+Flashrom support: n
+Release year: 2012
diff --git a/src/mainboard/dell/latitude_e6230/devicetree.cb b/src/mainboard/dell/latitude_e6230/devicetree.cb
new file mode 100644
index 0000000000..77c51ef480
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/devicetree.cb
@@ -0,0 +1,115 @@
+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x000009e9"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax
+ device lapic 0x0 on end
+ device lapic 0xacac off end
+
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ end
+ end
+ device domain 0x0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x005c0921"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x00000000"
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x31"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+ device pci 14.0 on # USB 3.0 Controller
+ subsystemid 0x1028 0x0532
+ end
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x1028 0x0532
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 on # Intel Gigabit Ethernet
+ subsystemid 0x1028 0x0532
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x1028 0x0532
+ end
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x1028 0x0532
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x1028 0x0532
+ end
+ device pci 1c.1 on # PCIe Port #2
+ subsystemid 0x1028 0x0532
+ end
+ device pci 1c.2 on # PCIe Port #3
+ subsystemid 0x1028 0x0532
+ end
+ device pci 1c.3 on # PCIe Port #4
+ subsystemid 0x1028 0x0532
+ end
+ device pci 1c.4 off # PCIe Port #5
+ end
+ device pci 1c.5 on # PCIe Port #6
+ subsystemid 0x1028 0x0532
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x1028 0x0532
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x1028 0x0532
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x1028 0x0532
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x1028 0x0532
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x1028 0x0532
+ end
+ device pci 01.0 off # PCIe Bridge for discrete graphics
+ end
+ device pci 02.0 on # Internal graphics VGA controller
+ subsystemid 0x1028 0x0532
+ end
+ end
+end
diff --git a/src/mainboard/dell/latitude_e6230/dsdt.asl b/src/mainboard/dell/latitude_e6230/dsdt.asl
new file mode 100644
index 0000000000..15c538d286
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/dsdt.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20141018 // OEM revision
+)
+{
+ #include <southbridge/intel/common/acpi/platform.asl>
+
+ #include "acpi/platform.asl"
+
+ /* global NVS and variables. */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ }
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/dell/latitude_e6230/gpio.c b/src/mainboard/dell/latitude_e6230/gpio.c
new file mode 100644
index 0000000000..d960139b5c
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/gpio.c
@@ -0,0 +1,208 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_OUTPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio17 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/latitude_e6230/hda_verb.c b/src/mainboard/dell/latitude_e6230/hda_verb.c
new file mode 100644
index 0000000000..381f29ad54
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/hda_verb.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
+ 0x10280532, /* Subsystem ID */
+
+ 0x0000000b, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x0, 0x10280532),
+
+ /* NID 0x0a. */
+ AZALIA_PIN_CFG(0x0, 0x0a, 0x03a11020),
+
+ /* NID 0x0b. */
+ AZALIA_PIN_CFG(0x0, 0x0b, 0x0321101f),
+
+ /* NID 0x0c. */
+ AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0),
+
+ /* NID 0x0d. */
+ AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110),
+
+ /* NID 0x0e. */
+ AZALIA_PIN_CFG(0x0, 0x0e, 0x23011050),
+
+ /* NID 0x0f. */
+ AZALIA_PIN_CFG(0x0, 0x0f, 0x23a1102e),
+
+ /* NID 0x10. */
+ AZALIA_PIN_CFG(0x0, 0x10, 0x400000f3),
+
+ /* NID 0x11. */
+ AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30130),
+
+ /* NID 0x1f. */
+ AZALIA_PIN_CFG(0x0, 0x1f, 0x400000f0),
+
+ /* NID 0x20. */
+ AZALIA_PIN_CFG(0x0, 0x20, 0x400000f0),
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+
+ 0x00000004, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+ /* NID 0x05. */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+
+ /* NID 0x06. */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
+
+ /* NID 0x07. */
+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/latitude_e6230/mainboard.c b/src/mainboard/dell/latitude_e6230/mainboard.c
new file mode 100644
index 0000000000..cfae7d98f5
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/mainboard.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/dell/latitude_e6230/romstage.c b/src/mainboard/dell/latitude_e6230/romstage.c
new file mode 100644
index 0000000000..42456f63a4
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/romstage.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci_ops.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/dell/mec5055/mec5055.h>
+#include <superio/smsc/ece5048/ece5048.h>
+
+void mainboard_pch_lpc_setup(void)
+{
+ /* port 0x910 and 0x911 is needed to initialize the EC */
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x007c0901);
+}
+
+void mainboard_late_rcba_config(void)
+{
+ RCBA32(BUC) = 0x00000010;
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 0, 1 },
+ { 1, 2, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 1, 3 },
+ { 1, 2, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 2, 6 },
+ { 1, 0, 6 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+ ece5048_early_init(0x94e);
+ mec5055_early_init();
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+}
diff --git a/src/mainboard/dell/latitude_e6230/smihandler.c b/src/mainboard/dell/latitude_e6230/smihandler.c
new file mode 100644
index 0000000000..7ed83bc469
--- /dev/null
+++ b/src/mainboard/dell/latitude_e6230/smihandler.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <stdint.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5055/mec5055.h>
+
+int mainboard_smi_apmc(u8 data)
+{
+ switch (data) {
+ case APM_CNT_ACPI_ENABLE:
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x007c0901);
+ mec5055_ec_acpi_enable();
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x005c0921);
+ default:
+ break;
+ }
+ return 0;
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 21:19:22 +0000