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+# HP EliteBook Folio 9480m
+
+This page is about the notebook [HP EliteBook Folio 9480m].
+
+## Release status
+
+HP EliteBook Folio 9480m was released in 2013 and is now end of life.
+It can be bought from a secondhand market like Taobao or eBay.
+
+## Required proprietary blobs
+
+The following blobs are required to operate the hardware:
+1. EC firmware
+2. Intel ME firmware
+3. mrc.bin
+
+HP EliteBook Folio 9480m uses SMSC MEC1322 as its embedded controller.
+The EC firmware is stored in the flash chip, but we don't need to touch it,
+and we don't need it when building coreboot.
+
+Intel ME firmware is in the flash chip. It is not needed when building coreboot.
+
+The Haswell memory reference code binary (mrc.bin) is needed when building coreboot.
+We need to extract one from a Haswell Chromebook.
+
+## Programming
+
+HP EliteBook Folio 9480m has two flash chips. According to the strings found in the
+EC firmware, the 16MB chip which stores the BIOS image is called the system flash,
+and the 2MB chip which stores part of the system flash content is called the
+private flash.
+
+Before flashing, remove the battery and the hard drive cover.
+
+(TBD: pictures needed)
+
+To access the system flash. We need to connect the AC adapter to the machine,
+then clip on the flash chip with an SOIC-8 clip. If the programmer still cannot
+find the flash chip, you can first clip on the chip with the flash programmer
+disconnected with the host machine, plug in the AC adapter, then connect the
+programmer with the host machine. An [STM32-based flash programmer] is tested to work.
+
+To access the private flash chip. You can use a ch341a based flash programmer with
+the AC adapter disconnected.
+
+The firmware of this laptop is protected by [HP Sure Start]. We need to bypass
+this protection by doing the following:
+
+1. Erase the private flash, so the IFD protection will be disabled
+2. Modify the IFD to shrink the BIOS region, so that we'll not use or override
+   the protected bootblock and PEI region
+
+It works with the flash chip size set to 12MB in coreboot configuration, and the
+following flash layout in the modified IFD:
+
+  00000000:00000fff fd
+  00600000:00bfffff bios
+  00003000:005fffff me
+  00001000:00002fff gbe
+
+## Debugging
+
+The board can be debugged with EHCI debug. The EHCI debug port is the left USB port.
+
+## Test status
+
+(TBD...)
+
+- libgfxinit
+- SeaBIOS payload
+- SATA and M.2 SATA disk
+- EC firmware version XXX from OEM firmware version XXX
+- mrc.bin version 1.6.1 Build 2
+
+## Technology
+
+```eval_rst
++------------------+-----------------------------+
+| CPU              | Intel Haswell-ULT           |
++------------------+-----------------------------+
+| PCH              | Intel Lynx Point Low Power  |
++------------------+-----------------------------+
+| EC               | SMSC MEC1322                |
++------------------+-----------------------------+
+| Coprocessor      | Intel Management Engine     |
++------------------+-----------------------------+
+```
+
+[HP EliteBook Folio 9480m]: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7089926
+[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c05228980
+[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog
+[HP Sure Start]: http://h10032.www1.hp.com/ctg/Manual/c05163901