diff options
Diffstat (limited to 'src/soc/amd')
-rw-r--r-- | src/soc/amd/picasso/chip.c | 2 | ||||
-rw-r--r-- | src/soc/amd/picasso/cpu.c | 4 | ||||
-rw-r--r-- | src/soc/amd/picasso/include/soc/cpu.h | 3 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/chip.c | 2 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/cpu.c | 4 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/include/soc/cpu.h | 3 |
6 files changed, 6 insertions, 12 deletions
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 7c6e6fb967..dc661d2be3 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -20,7 +20,7 @@ extern const char *i2c_acpi_name(const struct device *dev); struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = picasso_init_cpus, + .init = mp_cpu_bus_init, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 55f9014c8f..3512c94d95 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -92,10 +92,10 @@ static const struct mp_ops mp_ops = { .post_mp_init = enable_smi_generation, }; -void picasso_init_cpus(struct device *dev) +void mp_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + if (mp_init_with_smm(cpu_bus, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); /* The flash is now no longer cacheable. Reset to WP for performance. */ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index d413c7293f..99b31c3bfe 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -3,11 +3,8 @@ #ifndef __PICASSO_CPU_H__ #define __PICASSO_CPU_H__ -#include <device/device.h> - #define CSTATE_BASE_REG 0xc0010073 -void picasso_init_cpus(struct device *dev); int get_cpu_count(void); void check_mca(void); diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 41fcafbab9..909b84793e 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -25,7 +25,7 @@ extern const char *i2c_acpi_name(const struct device *dev); struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = stoney_init_cpus, + .init = mp_cpu_bus_init, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 36583a50ea..9189cfb8c1 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -93,10 +93,10 @@ static const struct mp_ops mp_ops = { .post_mp_init = enable_smi_generation, }; -void stoney_init_cpus(struct device *dev) +void mp_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + if (mp_init_with_smm(cpu_bus, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); /* The flash is now no longer cacheable. Reset to WP for performance. */ diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index ea51f76a3e..8d25fb6d4e 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -3,8 +3,6 @@ #ifndef __STONEYRIDGE_CPU_H__ #define __STONEYRIDGE_CPU_H__ -#include <device/device.h> - /* * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest * numbered registers. Any values defined below are subtracted from the @@ -16,7 +14,6 @@ #define SOC_EARLY_VMTRR_CAR_HEAP 2 #define SOC_EARLY_VMTRR_TEMPRAM 3 -void stoney_init_cpus(struct device *dev); void check_mca(void); #endif /* __STONEYRIDGE_CPU_H__ */ |