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-rw-r--r--src/soc/intel/apollolake/lpc.c4
-rw-r--r--src/soc/intel/cannonlake/lpc.c4
-rw-r--r--src/soc/intel/common/block/include/intelblocks/lpc_lib.h9
-rw-r--r--src/soc/intel/common/block/lpc/lpc.c60
-rw-r--r--src/soc/intel/common/block/pmc/pmc.c4
-rw-r--r--src/soc/intel/skylake/lpc.c4
6 files changed, 55 insertions, 30 deletions
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index 95b8bf5fb7..70b29b5a42 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corp.
+ * Copyright (C) 2017-2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -82,7 +82,7 @@ void lpc_configure_pads(void)
gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios));
}
-void lpc_init(struct device *dev)
+void lpc_soc_init(struct device *dev)
{
const struct soc_intel_apollolake_config *cfg;
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index d0253edf30..60729f144a 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -181,7 +181,7 @@ static void clock_gate_8254(const struct device *dev)
itss_clock_gate_8254();
}
-void lpc_init(struct device *dev)
+void lpc_soc_init(struct device *dev)
{
/* Legacy initialization */
isa_dma_init();
diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index 2b525cab41..554c75d509 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corp.
+ * Copyright (C) 2017-2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -71,7 +71,9 @@ void lpc_open_mmio_window(uintptr_t base, size_t size);
bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size);
/* Init SoC Spcific LPC features. Common definition will be weak and
each soc will need to define the init. */
-void lpc_init(struct device *dev);
+void lpc_soc_init(struct device *dev);
+/* Fill up LPC IO resource structure inside SoC directory */
+void pch_lpc_soc_fill_io_resources(struct device *dev);
/* Init LPC GPIO pads */
void lpc_configure_pads(void);
/* Get SoC speicific MMIO ranges */
@@ -102,5 +104,8 @@ void soc_get_gen_io_dec_range(const struct device *dev,
uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]);
/* Mirror generic IO decoder range register settings into DMI PCR. */
void soc_setup_dmi_pcr_io_dec(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]);
+/* Add resource into LPC PCI device space */
+void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
+ uintptr_t base, size_t size, unsigned long flags);
#endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index 6b886e3fa4..55329550ab 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corp.
+ * Copyright (C) 2017-2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,32 +21,52 @@
#include <intelblocks/lpc_lib.h>
#include <soc/pm.h>
+/* SoC overrides */
+
/* Common weak definition, needs to be implemented in each soc LPC driver. */
-__attribute__((weak)) void lpc_init(struct device *dev) { /* no-op */ }
+__attribute__((weak)) void lpc_soc_init(struct device *dev)
+{
+ /* no-op */
+}
-static void soc_lpc_add_io_resources(device_t dev)
+/* Fill up LPC IO resource structure inside SoC directory */
+__attribute__((weak)) void pch_lpc_soc_fill_io_resources(struct device *dev)
+{
+ /* no-op */
+}
+
+void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
+ uintptr_t base, size_t size, unsigned long flags)
{
struct resource *res;
+ res = new_resource(dev, offset);
+ res->base = base;
+ res->size = size;
+ res->flags = flags;
+}
+static void pch_lpc_add_io_resources(device_t dev)
+{
/* Add the default claimed legacy IO range for the LPC device. */
- res = new_resource(dev, 0);
- res->base = 0;
- res->size = 0x1000;
- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ pch_lpc_add_new_resource(dev, 0, 0, 0x1000, IORESOURCE_IO |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED);
+
+ /* SoC IO resource overrides */
+ pch_lpc_soc_fill_io_resources(dev);
}
-static void soc_lpc_read_resources(device_t dev)
+static void pch_lpc_read_resources(device_t dev)
{
/* Get the PCI resources of this device. */
pci_dev_read_resources(dev);
/* Add IO resources to LPC. */
- soc_lpc_add_io_resources(dev);
+ pch_lpc_add_io_resources(dev);
}
-static void set_child_resources(struct device *dev);
+static void pch_lpc_set_child_resources(struct device *dev);
-static void loop_resources(struct device *dev)
+static void pch_lpc_loop_resources(struct device *dev)
{
struct resource *res;
@@ -62,39 +82,39 @@ static void loop_resources(struct device *dev)
lpc_open_mmio_window(res->base, res->size);
}
}
- set_child_resources(dev);
+ pch_lpc_set_child_resources(dev);
}
/*
* Loop through all the child devices' resources, and open up windows to the
* LPC bus, as appropriate.
*/
-static void set_child_resources(struct device *dev)
+static void pch_lpc_set_child_resources(struct device *dev)
{
struct bus *link;
struct device *child;
for (link = dev->link_list; link; link = link->next) {
for (child = link->children; child; child = child->sibling)
- loop_resources(child);
+ pch_lpc_loop_resources(child);
}
}
-static void set_resources(device_t dev)
+static void pch_lpc_set_resources(device_t dev)
{
pci_dev_set_resources(dev);
/* Now open up windows to devices which have declared resources. */
- set_child_resources(dev);
+ pch_lpc_set_child_resources(dev);
}
static struct device_operations device_ops = {
- .read_resources = soc_lpc_read_resources,
- .set_resources = set_resources,
+ .read_resources = pch_lpc_read_resources,
+ .set_resources = pch_lpc_set_resources,
.enable_resources = pci_dev_enable_resources,
.write_acpi_tables = southbridge_write_acpi_tables,
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
- .init = lpc_init,
+ .init = lpc_soc_init,
.scan_bus = scan_lpc_bus,
.ops_pci = &pci_dev_ops_pci,
};
@@ -122,7 +142,7 @@ static const unsigned short pci_device_ids[] = {
0
};
-static const struct pci_driver soc_lpc __pci_driver = {
+static const struct pci_driver pch_lpc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index e1efe4641f..f668ea01fd 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -111,7 +111,7 @@ static const unsigned short pci_device_ids[] = {
0
};
-static const struct pci_driver pch_lpc __pci_driver = {
+static const struct pci_driver pch_pmc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index 9cd450b862..d0678c93fb 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -115,7 +115,7 @@ static void clock_gate_8254(struct device *dev)
itss_clock_gate_8254();
}
-void lpc_init(struct device *dev)
+void lpc_soc_init(struct device *dev)
{
/* Legacy initialization */
isa_dma_init();
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 21:52:11 +0000