diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/sram.h | 24 | ||||
| -rw-r--r-- | src/soc/intel/common/block/sram/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/sram/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/sram/sram.c | 58 |
4 files changed, 87 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/sram.h b/src/soc/intel/common/block/include/intelblocks/sram.h new file mode 100644 index 0000000000..5b1d902213 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/sram.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_SRAM_H +#define SOC_INTEL_COMMON_BLOCK_SRAM_H + +#include <device/device.h> + +/* This function is specific to soc and defined as common weak function */ +void soc_sram_init(struct device *dev); + +#endif /* SOC_INTEL_COMMON_BLOCK_SRAM_H */ diff --git a/src/soc/intel/common/block/sram/Kconfig b/src/soc/intel/common/block/sram/Kconfig new file mode 100644 index 0000000000..bfd1a8a8eb --- /dev/null +++ b/src/soc/intel/common/block/sram/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_SRAM + bool + help + Intel Processor common SRAM support diff --git a/src/soc/intel/common/block/sram/Makefile.inc b/src/soc/intel/common/block/sram/Makefile.inc new file mode 100644 index 0000000000..a490d914fd --- /dev/null +++ b/src/soc/intel/common/block/sram/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SRAM) += sram.c diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c new file mode 100644 index 0000000000..05fc5c736b --- /dev/null +++ b/src/soc/intel/common/block/sram/sram.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/sram.h> +#include <soc/iomap.h> + +__attribute__((weak)) void soc_sram_init(struct device *dev) { /* no-op */ } + +static void sram_read_resources(struct device *dev) +{ + struct resource *res; + pci_dev_read_resources(dev); + + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = SRAM_BASE_0; + res->size = SRAM_SIZE_0; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, PCI_BASE_ADDRESS_2); + res->base = SRAM_BASE_2; + res->size = SRAM_SIZE_2; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static const struct device_operations device_ops = { + .read_resources = sram_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = soc_sram_init, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_APL_SRAM, + PCI_DEVICE_ID_INTEL_GLK_SRAM, + 0, +}; + +static const struct pci_driver sram __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; |