diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 3 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 507290f504..f08fd0a95e 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -130,6 +130,8 @@ struct soc_intel_cannonlake_config { uint16_t usb2_wake_enable_bitmap; /* Wake Enable Bitmap for USB3 ports */ uint16_t usb3_wake_enable_bitmap; + /* USB2 PHY power gating */ + uint8_t PchUsb2PhySusPgDisable; /* SATA related */ enum { diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 0713ef4604..dfc7e22522 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -273,6 +273,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } + if (config->PchUsb2PhySusPgDisable) + params->PchUsb2PhySusPgEnable = 0; + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |