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-rw-r--r--src/vendorcode/amd/agesa/common/agesa-entry-cfg.h8
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c2
-rw-r--r--src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc2
-rw-r--r--src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc2
-rw-r--r--src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc2
-rw-r--r--src/vendorcode/cavium/bdk/libdram/libdram.c6
-rw-r--r--src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-warn.h14
-rw-r--r--src/vendorcode/google/chromeos/acpi.c4
-rw-r--r--src/vendorcode/google/chromeos/acpi/chromeos.asl2
-rw-r--r--src/vendorcode/google/chromeos/chromeos.h8
-rw-r--r--src/vendorcode/google/chromeos/cr50_enable_update.c2
-rw-r--r--src/vendorcode/google/chromeos/elog.c4
-rw-r--r--src/vendorcode/google/chromeos/ramoops.c8
-rw-r--r--src/vendorcode/google/chromeos/sar.c4
-rw-r--r--src/vendorcode/google/chromeos/tpm2.c4
15 files changed, 36 insertions, 36 deletions
diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
index 33a2139c6b..f787014f96 100644
--- a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
+++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
@@ -8,18 +8,18 @@
#define AGESA_ENTRY_INIT_EARLY TRUE
#define AGESA_ENTRY_INIT_POST TRUE
-#define AGESA_ENTRY_INIT_RESUME IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#define AGESA_ENTRY_INIT_RESUME CONFIG(HAVE_ACPI_RESUME)
#else
#define AGESA_ENTRY_INIT_ENV TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#define AGESA_ENTRY_INIT_LATE_RESTORE CONFIG(HAVE_ACPI_RESUME)
#define AGESA_ENTRY_INIT_MID TRUE
#define AGESA_ENTRY_INIT_LATE TRUE
#define AGESA_ENTRY_INIT_S3SAVE \
- (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) || \
- IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
+ (CONFIG(HAVE_ACPI_RESUME) || \
+ CONFIG(ENABLE_MRC_CACHE))
#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
index b4a60a1201..3bf35f1c76 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
@@ -489,7 +489,7 @@ MemPIsIdSupported (
return TRUE;
}
}
- if (IS_ENABLED(CONFIG_FORCE_AM1_SOCKET_SUPPORT))
+ if (CONFIG(FORCE_AM1_SOCKET_SUPPORT))
return TRUE;
else
return FALSE;
diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
index 51c6b52248..75ba9e7df5 100644
--- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
@@ -916,7 +916,7 @@ fam15_disable_stack_remote_read_exit:
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
-#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
+#if !CONFIG(POSTCAR_STAGE)
wbinvd
#else
invd
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
index b9cc39fac5..8f3ca83598 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
@@ -651,7 +651,7 @@ fam15_disable_stack_remote_read_exit:
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
-#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
+#if !CONFIG(POSTCAR_STAGE)
wbinvd
#else
invd
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
index 6c4ad596e1..357b8be6d5 100644
--- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
@@ -615,7 +615,7 @@ fam16_disable_stack_remote_read_exit:
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
-#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
+#if !CONFIG(POSTCAR_STAGE)
wbinvd
#else
invd
diff --git a/src/vendorcode/cavium/bdk/libdram/libdram.c b/src/vendorcode/cavium/bdk/libdram/libdram.c
index 9b2f2e871e..214aa05b24 100644
--- a/src/vendorcode/cavium/bdk/libdram/libdram.c
+++ b/src/vendorcode/cavium/bdk/libdram/libdram.c
@@ -149,9 +149,9 @@ static void bdk_dram_disable_ecc_reporting(bdk_node_t node)
static int bdk_libdram_tune_node(int node)
{
int errs, tot_errs;
- int do_dllro_hw = IS_ENABLED(CONFIG_CAVIUM_BDK_DDR_TUNE_HW_OFFSETS);
- int do_dllwo = IS_ENABLED(CONFIG_CAVIUM_BDK_DDR_TUNE_WRITE_OFFSETS);
- int do_eccdll = IS_ENABLED(CONFIG_CAVIUM_BDK_DDR_TUNE_ECC_ENABLE);
+ int do_dllro_hw = CONFIG(CAVIUM_BDK_DDR_TUNE_HW_OFFSETS);
+ int do_dllwo = CONFIG(CAVIUM_BDK_DDR_TUNE_WRITE_OFFSETS);
+ int do_eccdll = CONFIG(CAVIUM_BDK_DDR_TUNE_ECC_ENABLE);
BDK_CSR_INIT(lmc_config, node, BDK_LMCX_CONFIG(0)); // FIXME: probe LMC0
do_eccdll = (lmc_config.s.ecc_ena != 0); // change to ON if ECC enabled
diff --git a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-warn.h b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-warn.h
index 84f9c3b55a..82b8ea0b11 100644
--- a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-warn.h
+++ b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-warn.h
@@ -103,19 +103,19 @@ typedef enum
*/
#define BDK_TRACE(area, format, ...) do { \
if ((BDK_TRACE_ENABLE_INIT == BDK_TRACE_ENABLE_##area && \
- IS_ENABLED(CONFIG_CAVIUM_BDK_VERBOSE_INIT)) || \
+ CONFIG(CAVIUM_BDK_VERBOSE_INIT)) || \
(BDK_TRACE_ENABLE_DRAM == BDK_TRACE_ENABLE_##area && \
- IS_ENABLED(CONFIG_CAVIUM_BDK_VERBOSE_DRAM)) || \
+ CONFIG(CAVIUM_BDK_VERBOSE_DRAM)) || \
(BDK_TRACE_ENABLE_DRAM_TEST == BDK_TRACE_ENABLE_##area && \
- IS_ENABLED(CONFIG_CAVIUM_BDK_VERBOSE_DRAM_TEST)) || \
+ CONFIG(CAVIUM_BDK_VERBOSE_DRAM_TEST)) || \
(BDK_TRACE_ENABLE_QLM == BDK_TRACE_ENABLE_##area && \
- IS_ENABLED(CONFIG_CAVIUM_BDK_VERBOSE_QLM)) || \
+ CONFIG(CAVIUM_BDK_VERBOSE_QLM)) || \
(BDK_TRACE_ENABLE_PCIE_CONFIG == BDK_TRACE_ENABLE_##area && \
- IS_ENABLED(CONFIG_CAVIUM_BDK_VERBOSE_PCIE_CONFIG)) || \
+ CONFIG(CAVIUM_BDK_VERBOSE_PCIE_CONFIG)) || \
(BDK_TRACE_ENABLE_PCIE == BDK_TRACE_ENABLE_##area && \
- IS_ENABLED(CONFIG_CAVIUM_BDK_VERBOSE_PCIE)) || \
+ CONFIG(CAVIUM_BDK_VERBOSE_PCIE)) || \
(BDK_TRACE_ENABLE_PHY == BDK_TRACE_ENABLE_##area && \
- IS_ENABLED(CONFIG_CAVIUM_BDK_VERBOSE_PHY))) \
+ CONFIG(CAVIUM_BDK_VERBOSE_PHY))) \
printk(BIOS_DEBUG, #area ": " format, ##__VA_ARGS__); \
} while (0)
diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c
index 8fd47a6a76..59c4901754 100644
--- a/src/vendorcode/google/chromeos/acpi.c
+++ b/src/vendorcode/google/chromeos/acpi.c
@@ -14,7 +14,7 @@
*/
#include <arch/acpigen.h>
-#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB)
+#if CONFIG(GENERIC_GPIO_LIB)
#include <gpio.h>
#endif
#include "chromeos.h"
@@ -33,7 +33,7 @@ void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num)
acpigen_write_integer(gpios[i].type);
acpigen_write_integer(gpios[i].polarity);
gpio_num = gpios[i].gpio_num;
-#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB)
+#if CONFIG(GENERIC_GPIO_LIB)
/* Get ACPI pin from GPIO library if available */
if (gpios[i].gpio_num != CROS_GPIO_VIRTUAL)
gpio_num = gpio_acpi_pin(gpio_num);
diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl
index d813b22ac0..4852600748 100644
--- a/src/vendorcode/google/chromeos/acpi/chromeos.asl
+++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl
@@ -15,7 +15,7 @@
#include <security/vboot/vbnv_layout.h>
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* GPIO package generated at run time. */
External (OIPG)
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index 6831261dc5..6db7fc44dd 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -24,7 +24,7 @@
#include <security/vboot/misc.h>
#include <security/vboot/vboot_common.h>
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* functions implemented in watchdog.c */
void mark_watchdog_tombstone(void);
void reboot_from_watchdog(void);
@@ -44,9 +44,9 @@ struct romstage_handoff;
#include "gnvs.h"
struct device;
-#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
+#if CONFIG(CHROMEOS_RAMOOPS)
void chromeos_ram_oops_init(chromeos_acpi_t *chromeos);
-#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS_DYNAMIC)
+#if CONFIG(CHROMEOS_RAMOOPS_DYNAMIC)
static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {}
#else /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */
void chromeos_reserve_ram_oops(struct device *dev, int idx);
@@ -70,7 +70,7 @@ void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num);
* ACPI-specific Chrome OS needs.
*/
void mainboard_chromeos_acpi_generate(void);
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
void chromeos_dsdt_generator(struct device *dev);
#else
#define chromeos_dsdt_generator DEVICE_NOOP
diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c
index 660fe2e86f..91a10cb9aa 100644
--- a/src/vendorcode/google/chromeos/cr50_enable_update.c
+++ b/src/vendorcode/google/chromeos/cr50_enable_update.c
@@ -153,7 +153,7 @@ static void enable_update(void *unused)
/* clear current post code avoid chatty eventlog on subsequent boot*/
post_code(0);
- if (IS_ENABLED(CONFIG_POWER_OFF_ON_CR50_UPDATE))
+ if (CONFIG(POWER_OFF_ON_CR50_UPDATE))
poweroff();
halt();
}
diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c
index fbbfd16196..17cb4d9018 100644
--- a/src/vendorcode/google/chromeos/elog.c
+++ b/src/vendorcode/google/chromeos/elog.c
@@ -18,7 +18,7 @@
#include <elog.h>
#include <security/vboot/vboot_common.h>
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
#include <arch/acpi.h>
#endif
@@ -41,7 +41,7 @@ static void elog_add_boot_reason(void *unused)
if (dev) {
int log_event = 1;
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
/* Skip logging developer mode in ACPI resume path */
if (acpi_is_wakeup())
log_event = 0;
diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c
index c72af00c54..7eef2d1338 100644
--- a/src/vendorcode/google/chromeos/ramoops.c
+++ b/src/vendorcode/google/chromeos/ramoops.c
@@ -23,7 +23,7 @@
#include <device/device.h>
#include "chromeos.h"
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
static void set_ramoops(chromeos_acpi_t *chromeos, void *ram_oops, size_t size)
{
@@ -42,7 +42,7 @@ static void reserve_ram_oops_dynamic(chromeos_acpi_t *chromeos)
const size_t size = CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE;
void *ram_oops;
- if (!IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS_DYNAMIC))
+ if (!CONFIG(CHROMEOS_RAMOOPS_DYNAMIC))
return;
ram_oops = cbmem_add(CBMEM_ID_RAM_OOPS, size);
@@ -50,7 +50,7 @@ static void reserve_ram_oops_dynamic(chromeos_acpi_t *chromeos)
set_ramoops(chromeos, ram_oops, size);
}
-#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS_DYNAMIC)
+#if CONFIG(CHROMEOS_RAMOOPS_DYNAMIC)
static inline void set_global_chromeos_pointer(chromeos_acpi_t *chromeos) {}
#else /* !CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */
@@ -96,7 +96,7 @@ void chromeos_ram_oops_init(chromeos_acpi_t *chromeos)
reserve_ram_oops_dynamic(chromeos);
}
-#elif IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS_NON_ACPI)
+#elif CONFIG(CHROMEOS_RAMOOPS_NON_ACPI)
static void ramoops_alloc(void *arg)
{
diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c
index 417b9b6744..bbcb211c3a 100644
--- a/src/vendorcode/google/chromeos/sar.c
+++ b/src/vendorcode/google/chromeos/sar.c
@@ -74,7 +74,7 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits)
sar_expected_len = buffer_size;
bin_buff_adjusted_size = sizeof(struct wifi_sar_limits);
- if (!IS_ENABLED(CONFIG_GEO_SAR_ENABLE)) {
+ if (!CONFIG(GEO_SAR_ENABLE)) {
sar_expected_len = buffer_size -
sizeof(struct wifi_sar_delta_table) *
sizeof(uint8_t) * 2;
@@ -88,7 +88,7 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits)
printk(BIOS_ERR, "Error: Could not locate '%s' in VPD.\n",
wifi_sar_limit_key);
- if (!IS_ENABLED(CONFIG_WIFI_SAR_CBFS))
+ if (!CONFIG(WIFI_SAR_CBFS))
return -1;
printk(BIOS_DEBUG, "Checking CBFS for default SAR values\n");
diff --git a/src/vendorcode/google/chromeos/tpm2.c b/src/vendorcode/google/chromeos/tpm2.c
index d4816e09f9..08e8ddb995 100644
--- a/src/vendorcode/google/chromeos/tpm2.c
+++ b/src/vendorcode/google/chromeos/tpm2.c
@@ -22,10 +22,10 @@ static void disable_platform_hierarchy(void *unused)
{
int ret;
- if (!IS_ENABLED(CONFIG_TPM2))
+ if (!CONFIG(TPM2))
return;
- if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT))
+ if (!CONFIG(RESUME_PATH_SAME_AS_BOOT))
return;
ret = tlcl_lib_init();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 17:10:37 +0000