| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-11-10 | arch/riscv: Pass cbmem_top to ramstage via calling argument | Arthur Heymans |
| 2019-08-06 | Documentation: Advertise support for OpenSBI | Patrick Rudolph |
| 2019-06-21 | Documentatioan: update stage handoff protocol | Xiang Wang |
| 2018-10-30 | Documentation/riscv: Improve `index.md` | Paul Menzel |
| 2018-09-15 | riscv: add documentation for stages and payloads | Ronald G. Minnich |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |