| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-03-06 | src/arch/riscv: Convert to SPDX license header | Patrick Georgi |
| 2019-11-10 | arch/riscv: Pass cbmem_top to ramstage via calling argument | Arthur Heymans |
| 2019-02-13 | riscv: Add initial support for 32bit boards | Philipp Hug |
| 2018-11-05 | riscv: add support to block smp in each stage | Xiang Wang |
| 2018-10-06 | arch/riscv: Update comment about mstatus initialization | Jonathan Neuschäfer |
| 2018-09-05 | riscv: add entry assembly file for RAMSTAGE | Xiang Wang |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |