| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-11-06 | arch/riscv: Rename `stages.c` to `romstage.c` | Nico Huber |
| 2019-07-28 | riscv: Remove unused headers | Patrick Rudolph |
| 2019-02-02 | riscv: Simplify payload handling | Xiang Wang |
| 2019-01-16 | buildsystem: Promote rules.h to default include | Kyösti Mälkki |
| 2018-11-05 | riscv: add support to block smp in each stage | Xiang Wang |
| 2018-02-20 | arch/riscv: Pass the bootrom-provided FDT to the payload | Jonathan Neuschäfer |
| 2016-02-11 | arch: remove stage_exit() | Aaron Durbin |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2014-12-01 | Add UCB RISCV support for architecture, soc, and emulation mainboard.. | Ronald G. Minnich |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |