coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-03-06	src/arch/riscv: Convert to SPDX license header	Patrick Georgi
2019-08-03	riscv: add support for OpenSBI	Xiang Wang
2016-04-21	lib: add common write_tables() implementation	Aaron Durbin
2016-04-21	lib/coreboot_table: add architecture hooks for adding tables	Aaron Durbin
2016-04-21	lib/bootmem: allow architecture specific bootmem ranges	Aaron Durbin
2016-04-21	arch: only print cbmem entries in one place	Aaron Durbin
2016-04-21	arch: use Kconfig variable for coreboot table size	Aaron Durbin
2016-04-21	arch/riscv/tables: remove confusion over write_tables()	Aaron Durbin
2016-02-19	lib/coreboot_table: add function to allow arch code to add records	Aaron Durbin
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-01-27	CBMEM: Implement cbmem_run_init_hooks() stub	Kyösti Mälkki
2014-12-09	UCB RISCV: Switch to DYNAMIC_CBMEM	Kyösti Mälkki
2014-12-01	Add UCB RISCV support for architecture, soc, and emulation mainboard..	Ronald G. Minnich