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Some coreboot project code with my work
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x86
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pci_ops_conf1.c
Age
Commit message (
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Author
2019-03-16
device/pci_ops: Have only default PCI bus ops available
Kyösti Mälkki
2019-03-16
device/pci_ops: Reuse romstage PCI config for ramstage
Kyösti Mälkki
2019-03-13
device/pci_ops: Rename 'where' to 'reg'
Kyösti Mälkki
2019-03-13
device/pci_ops: Unify signatures
Kyösti Mälkki
2019-03-08
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
Julius Werner
2019-03-06
device/pci_ops: Change ramstage PCI accessor signatures
Kyösti Mälkki
2019-03-03
device/pci_ops: Drop unused parameter
Kyösti Mälkki
2019-01-28
src: Don't use a #defines like Kconfig symbols
Elyes HAOUAS
2018-06-04
arch/x86: Remove unneeded includes
Elyes HAOUAS
2017-07-13
src: add IS_ENABLED() around Kconfig symbol references
Martin Roth
2017-03-17
arch/x86: Wrap lines at 80 columns
Lee Leahy
2017-03-17
arch/x86: Fix space issues detected by checkpatch
Lee Leahy
2016-01-26
arch/x86: Drop arch/pciconf.h
Stefan Reinauer
2016-01-14
arch/x86: add missing license headers
Martin Roth
2015-07-13
x86: flatten hierarchy
Stefan Reinauer