coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2017-09-06	AGESA: Rename assembly from .inc to .S	Kyösti Mälkki
2017-07-15	vendorcode/amd/agesa: Tidy up gcccar.inc	Kyösti Mälkki
2017-06-28	cpu/*: Add whitespace around '<<'	Elyes HAOUAS
2017-04-05	AGESA: Disable CAR with empty stack	Kyösti Mälkki
2017-04-05	AGESA: BIST is already preserved	Kyösti Mälkki
2017-04-05	AGESA: Move romstage main entry under cpu	Kyösti Mälkki
2017-04-05	AGESA: Move amd_initmmio() call	Kyösti Mälkki
2017-03-09	AGESA: Fix SSE regression and align stack early	Kyösti Mälkki
2016-11-25	AGESA binaryPI: Fix cache-as-ram for x86_64	Kyösti Mälkki
2016-07-31	src/cpu: Capitalize ROM and RAM	Elyes HAOUAS
2016-01-23	cpu/amd: remove .intel_syntax	Patrick Georgi
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-07-21	cpu: port amd/agesa to 64bit	Stefan Reinauer
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2013-12-07	Correct file permissions.	Idwer Vollering
2013-08-16	AMD AGESA: Remove INVD instruction when transitioning from CAR	Bruce Griffith
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-11-02	AMD agesa: add enable cache at the end of disable_cache_as_ram	Siyuan Wang
2012-04-25	Replace cache control magic numbers with symbols	Patrick Georgi
2012-04-16	S3 code in coreboot public folder.	zbao
2011-07-18	Add AMD Family 10 support to cpu folder	efdesign98