coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2019-01-13	aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK	Kyösti Mälkki
2018-08-17	intel/socket_mPGA604: Keep only model f2x	Kyösti Mälkki
2018-06-02	intel/socket_mPGA604 intel/e7505: Switch to POSTCAR_STAGE	Kyösti Mälkki
2018-06-02	cpu/intel/car: Prepare for some POSTCAR_STAGE support	Kyösti Mälkki
2016-06-21	intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP	Kyösti Mälkki
2016-06-18	intel/cache_as_ram_ht.inc: Fix include	Kyösti Mälkki
2015-05-04	cpu: get rid of socket source code	Stefan Reinauer
2014-07-17	cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2012-04-02	Apply cache-as-ram conditionally on socket mPGA604	Kyösti Mälkki
2010-09-30	Rename build system variables to be more intuitive, and	Patrick Georgi
2009-10-17	Remove some more instances of including previous empty x86/fpu/Makefile.inc	Peter Stuge
2009-10-16	Drop empty cpu/x86/{mmx,sse}/{Config.lb,Makefile.inc} and remove references	Peter Stuge
2009-09-25	some progress on kconfig:	Patrick Georgi