coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2019-11-15	nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK	Arthur Heymans
2019-11-15	nb/intel/x4x: Move boilerplate romstage to a common location	Arthur Heymans
2019-11-14	mb//(ich7/x4x): Use common early southbridge init	Arthur Heymans
2019-11-12	sb/intel/i82801gx: Add common LPC decode code	Arthur Heymans
2019-11-11	mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'	Elyes HAOUAS
2019-10-11	sb/intel/i82801gx: Move CIR init to a common place	Arthur Heymans
2019-08-26	soc/intel: Use common romstage code	Kyösti Mälkki
2019-08-18	cpu/intel: Enter romstage without BIST	Kyösti Mälkki
2019-04-23	src: Add missing include 'console.h'	Elyes HAOUAS
2019-04-13	sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB	Patrick Rudolph
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2019-01-10	mb/foxconn/g41s-k: Add g41m variant	Arthur Heymans
2019-01-10	mb: Move timestamp_add_now to northbridge x4x	Elyes HAOUAS
2019-01-09	cpu/intel: Use the common code to initialize the romstage timestamps	Arthur Heymans
2019-01-08	sb/intel/i82801gx: Autodisable functions based on devicetree	Arthur Heymans
2018-01-14	mb///romstage.c: Clean up targets with i82801gx	Arthur Heymans
2018-01-05	nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout	Arthur Heymans
2017-06-12	mb/foxconn/g41s-k: add new mainboard	Samuel Holland