coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-05-18	src: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-09	src/: Replace GPL boilerplate with SPDX headers	Patrick Georgi
2020-04-06	mb/google/gru: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	mainboard/google: Remove copyright notices	Patrick Georgi
2017-12-05	google/gru: update RAMID table	Lin Huang
2017-06-19	rockchip/rk3399: fix DRAM gate training issue	Lin Huang
2017-05-11	google/gru: support 800M/928M frequency for bob	Caesar Wang
2017-03-07	google/gru: add MAX_SDRAM_FREQ config to choose max ddr freq	Shunqian Zheng
2016-12-06	Bob: Update the memory ramid of bob	Shasha Zhao
2016-12-06	Bob: add bob in coreboot	Shasha Zhao
2016-11-17	google/gru: Move to one CA training pattern	Derek Basehore
2016-11-17	google/gru: Add new CA training pattern	Derek Basehore
2016-11-02	rockchip/rk3399: sdram: also prepare the index1 configuration	Lin Huang
2016-10-25	rockchip/rk3399: gru/kevin: drop unused sdram configs	Lin Huang
2016-10-07	google/gru: set W2W_DIFFCS_DLY to 5	Lin Huang
2016-10-06	rockchip: rk3399: improve write leveling flow	Jianqun Xu
2016-10-06	rockchip: rk3399: improve sdram noc timing	Lin Huang
2016-10-06	rockchip/rk3399: lower kevin board sdram frequency to 800MHz	Lin Huang
2016-08-27	gru: Make SDRAM parameters individual struct files in CBFS	Julius Werner