coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-05-06	soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel	Shaunak Saha
2020-04-06	mainboard/intel: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-23	mb/tglrvp: Update Audio AIC settings for Tiger Lake	Srinidhi N Kaushik
2020-03-18	mainboard/[g-p]*: Remove copyright notices	Patrick Georgi
2020-03-15	mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3	Srinidhi N Kaushik
2020-03-14	mb/intel/tglrvp: Update GPIO setting	Wonkyu Kim
2020-03-07	mb/intel/tglrvp: Add pin mux for Camera	Wonkyu Kim
2020-03-07	mb/intel/tglrvp: Update display ports for RVP	Wonkyu Kim
2020-03-06	mb/intel/tglrvp: Enable Audio AIC with Max98373 & ALC5682 on TGL	Srinidhi N Kaushik
2020-02-05	mb/intel/tglrvp: pin mux for ISH	Wonkyu Kim
2020-01-29	mb/intel/tglrvp: pin mux for image clocks	Wonkyu Kim
2020-01-27	mb/intel/tglrvp: Enable MIPI camera	Wonkyu Kim
2020-01-25	soc/intel/tigerlake: Fix GPIO communities	Shaunak Saha
2020-01-17	mb/tglrvp: update gpio pin mux for NVMe	Wonkyu Kim
2020-01-14	mb/intel/tglrvp: Add initial mainboard code	Ravi Sarawadi