index
:
coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
vimacs
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
mainboard
/
intel
/
tglrvp
/
variants
/
tglrvp_up4
Age
Commit message (
Expand
)
Author
2020-05-09
src/: Replace GPL boilerplate with SPDX headers
Patrick Georgi
2020-05-06
soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel
Shaunak Saha
2020-04-20
soc/intel/tigerlake: Update iDisp Link UPD settings
Srinidhi N Kaushik
2020-04-20
mb/tglrvp: Configure intel common config
Wonkyu Kim
2020-04-14
mb/intel/tglrvp : Enable RP LTR
Wonkyu Kim
2020-04-10
src/mb: Remove unneeded spaces before/after tabs
Elyes HAOUAS
2020-04-06
mainboard/intel: Use SPDX for GPL-2.0-only files
Angel Pons
2020-04-02
soc/intel/tigerlake: Reorganize memory initialization support
Furquan Shaikh
2020-03-30
tgl boards: Configure retimer Aux orientation
Brandon Breitenstein
2020-03-30
mb/tglrvp: Add GPE configuration
Shaunak Saha
2020-03-23
mb/tglrvp: Update Audio AIC settings for Tiger Lake
Srinidhi N Kaushik
2020-03-18
mainboard/[g-p]*: Remove copyright notices
Patrick Georgi
2020-03-16
mb/intel/tglrvp: Enable ISH driver and register firmware name
li feng
2020-03-14
mb/intel/tglrvp: Update GPIO setting
Wonkyu Kim
2020-03-11
mb/intel/tglrvp: Enable Hybrid storage mode
Wonkyu Kim
2020-03-11
mb/intel/tglrvp: sync up variant folders with latest up3
Wonkyu Kim
2020-03-10
mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation
Srinidhi N Kaushik
2020-03-09
mb/intel/tglrvp: Add memory config for Tiger Lake UP4
Srinidhi N Kaushik
2020-03-09
mb/intel/tglrvp: Add TGL UP4 RVP
Wonkyu Kim