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coreboot
2560p
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autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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amdmct
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mct_ddr3
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mctsrc.c
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Commit message (
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Author
2019-11-20
nb/amd/fam10: Drop support
Arthur Heymans
2019-08-10
src: Include <stdint.h> instead of <inttypes.h>
Jacob Garber
2019-07-02
src: Use CRx_TYPE type for CRx
Elyes HAOUAS
2018-11-12
src: Remove unneeded include "{arch,cpu}/cpu.h"
Elyes HAOUAS
2018-11-08
src: Replace common MSR addresses with macros
Elyes HAOUAS
2018-10-18
cpu/amd: Use common AMD's MSR
Elyes HAOUAS
2018-07-09
src/northbridge: Use "foo *bar" instead of "foo* bar"
Elyes HAOUAS
2018-06-14
src: Get rid of unneeded whitespace
Elyes HAOUAS
2017-01-11
amd/mct/ddr3: Correctly program maximum read latency
Timothy Pearson
2017-01-04
amdfam10: Perform major include ".c" cleanup
Damien Zammit
2016-10-09
northbridge/amd/amdmct/mct_ddr3: Remove commented code
Elyes HAOUAS
2016-09-21
northbridge/amd/amdmct: Improve code formatting
Elyes HAOUAS
2016-09-12
src/northbridge: Improve code formatting
Elyes HAOUAS
2016-08-31
northbridge/amd: Add required space before opening parenthesis '('
Elyes HAOUAS
2016-05-09
nb/amd/mct_ddr3: Add support for non-ECC DIMMs on AMD Family 15h
Timothy Pearson
2016-05-01
nb/amd/mct_ddr3: Warn if MaxRdLatency training fails on Family 15h
Timothy Pearson
2016-05-01
nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4
Timothy Pearson
2016-05-01
nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15h
Timothy Pearson
2016-04-22
nb/amd/mct_ddr3: Run fence training on each node after memory clock change
Timothy Pearson
2016-03-26
nb/amd/amdmct: Select max_lanes based on ECC presence or absence
Damien Zammit
2016-03-24
nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values
Timothy Pearson
2016-03-23
nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_...
Timothy Pearson
2016-03-12
nb/amd/mct_ddr3: Consolidate duplicated code
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetch
Timothy Pearson
2016-02-19
nb/amd/amdmct: Add socket specific configuration for FM2
Damien Zammit
2016-01-24
nb/amd/mct_ddr3: Add additional verbose-level debug statements
Timothy Pearson
2015-11-30
nb/amd/amdmct/mct_ddr3: Use StopOnError to decrease training time
Timothy Pearson
2015-11-23
amd/amdmct/mct_ddr3: Fix poor performance on Family 15h CPUs
Timothy Pearson
2015-11-16
northbridge/amd/mct_ddr3: Add registered and x4 DIMM support to Fam15h
Timothy Pearson
2015-11-16
amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10h
Timothy Pearson
2015-11-16
nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slots
Timothy Pearson
2015-11-15
northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot failure
Timothy Pearson
2015-11-02
cpu/amd: Add initial AMD Family 15h support
Timothy Pearson
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-26
northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalization
Timothy Pearson
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2013-06-03
northbridge/amd/amdmct: Use `static const` instead of `const static`
Paul Menzel
2013-03-01
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
Paul Menzel
2011-01-06
Fix some settings fo AMD MCT. It is based on BIOS test suite.
Zheng Bao
2010-12-02
More explicite and straight way to set seed.
Zheng Bao
2010-10-08
Trivial. Fix the typo.
Zheng Bao
2010-10-01
Trivial. Re-indent the code.
Zheng Bao
2010-08-30
Trivial syntax correction of AMD mct_ddr3 dir.
Kerry She
2010-04-23
DDR3 support for AMD Fam10.
Zheng Bao