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path: root/src/northbridge/intel/sandybridge/raminit_ivy.c
AgeCommit message (Expand)Author
2020-03-26nb/intel/sandybridge: Rename raminit_ivy.cAngel Pons
2020-03-26nb/intel/sandybridge: Unify the code pathsAngel Pons
2020-03-26nb/intel/sandybridge: Add print for PLL_REF100_CFGAngel Pons
2020-03-26nb/intel/sandybridge: Rewrite get_FRQAngel Pons
2020-03-25nb/intel/sandybridge: Cache FRQ indexAngel Pons
2020-03-25nb/intel/sandybridge: Rewrite table accessorsAngel Pons
2020-03-25nb/intel/sandybridge: Factor out timing tablesAngel Pons
2020-03-25nb/intel/sandybridge: Use SPDX headersAngel Pons
2020-03-23nb/intel/sandybridge: Use cached CPUIDAngel Pons
2020-03-18nb/intel/sandybridge: Tidy up code and commentsAngel Pons
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2020-01-10nb/intel/sandybridge: Add a bunch of MCHBAR definesAngel Pons
2020-01-09nb/intel/sandybridge: Make MCHBAR arithmetics consistentAngel Pons
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
2018-06-04northbridge/intel: Remove unneeded includesElyes HAOUAS
2018-04-16nb/intel/sandybridge: support more XMP timingsDan Elkouby
2017-06-12nb/intel/ivybridge: Improve CAS freq selectionArthur Heymans
2017-04-04nb/intel/sandybridge/raminit: Add default valuesPatrick Rudolph
2017-04-04nb/intel/sandybridge/raminit: Add 100MHz refclock supportPatrick Rudolph
2017-04-04nb/intel/sandybridge/raminit: Use Ivy Bridge specific valuesPatrick Rudolph
2017-03-27nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timingsArthur Heymans
2016-12-16nb/intel/sandybridge/raminit: Separate Sandybridge and IvybridgePatrick Rudolph
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