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coreboot
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broadwell_refcode
e6230
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mec1322
Some coreboot project code with my work
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northbridge
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intel
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sandybridge
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raminit_sandy.c
Age
Commit message (
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Author
2020-03-26
nb/intel/sandybridge: Drop dead code
Angel Pons
2020-03-25
nb/intel/sandybridge: Factor out timing tables
Angel Pons
2020-03-25
nb/intel/sandybridge: Use SPDX headers
Angel Pons
2020-03-23
nb/intel/sandybridge: Use cached CPUID
Angel Pons
2020-03-23
nb/intel/sandybridge: Remove oddball `- 1` in tRFC
Angel Pons
2020-03-18
nb/intel/sandybridge: Tidy up code and comments
Angel Pons
2020-03-17
src (minus soc and mainboard): Remove copyright notices
Patrick Georgi
2020-01-10
nb/intel/sandybridge: Add a bunch of MCHBAR defines
Angel Pons
2020-01-09
nb/intel/sandybridge: Make MCHBAR arithmetics consistent
Angel Pons
2018-06-04
northbridge/intel: Remove unneeded includes
Elyes HAOUAS
2018-04-16
nb/intel/sandybridge: support more XMP timings
Dan Elkouby
2017-06-12
nb/intel/sandybridge: Improve CAS freq selection
Arthur Heymans
2017-04-04
nb/intel/sandybridge/raminit: Use Ivy Bridge specific values
Patrick Rudolph
2017-03-27
nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings
Arthur Heymans
2016-12-16
nb/intel/sandybridge/raminit: Separate Sandybridge and Ivybridge
Patrick Rudolph