summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/x4x/Makefile.inc
AgeCommit message (Expand)Author
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2019-11-15nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
2019-11-15nb/intel/x4x: Move boilerplate romstage to a common locationArthur Heymans
2019-08-07northbridge/intel: Rename ram_calc.c to memmap.cKyösti Mälkki
2019-08-03intel/i945,gm45,pineview,x4x: Move stage cache support functionKyösti Mälkki
2019-01-24nb/intel/x4x: Put stage cache in TSEGArthur Heymans
2018-06-05nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans
2018-05-14nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans
2018-05-01nb/intel/x4x: Implement both read and write trainingArthur Heymans
2018-04-17nb/intel/x4x: Refactor setting default dll settingsArthur Heymans
2017-08-20nb/intel/x4x/raminit: Rework receive enable calibrationArthur Heymans
2017-02-17nb/intel/x4x: Implement resume from S3 suspendArthur Heymans
2016-05-31nb/intel/x4x: Add DMI/EP initDamien Zammit
2015-12-30northbridge/intel/x4x: Native raminitDamien Zammit
2015-12-29northbridge/intel/x4x: Intel 4-series northbridge supportDamien Zammit