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Some coreboot project code with my work
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intel
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x4x
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raminit_ddr2.c
Age
Commit message (
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Author
2018-05-14
nb/intel/x4x: Rename a things that are not specific to DDR2
Arthur Heymans
2018-05-14
nb/intel/x4x/raminit: Fix programming dual channel registers
Arthur Heymans
2018-05-01
nb/intel/x4x: Change memory layout to improve MTRR
Arthur Heymans
2018-05-01
nb/intel/x4x: Fix programming CxDRB
Arthur Heymans
2018-05-01
nb/intel/x4x: Implement both read and write training
Arthur Heymans
2018-04-17
nb/intel/x4x: Add a convenient macro to loop over bytelanes
Arthur Heymans
2018-04-17
nb/intel/x4x: Clarify the raminit memory mapping
Arthur Heymans
2018-04-17
nb/intel/x4x: Refactor setting default dll settings
Arthur Heymans
2018-04-17
nb/intel/x4x: Use SPI flash to cache raminit results
Arthur Heymans
2018-02-20
nb/x4x/raminit_ddr2: Refactor clock configuration slightly
Jonathan Neuschäfer
2017-12-16
nb/x4x/raminit: Rewrite SPD decode and timing selection
Arthur Heymans
2017-08-20
nb/intel/x4x: Fix booting with FSB800 DDR667 combination
Arthur Heymans
2017-08-20
nb/intel/x4x/raminit: Rework receive enable calibration
Arthur Heymans
2017-07-21
nb/intel/x4x: Rework programming DQ and DQS DLL timings
Arthur Heymans
2017-07-21
sb/intel/i82801jx: Add correct PCI ids and change names
Arthur Heymans
2017-05-24
nb/intel/x4x/raminit: Initialise async variable
Arthur Heymans
2017-05-22
nb/intel/x4x: Use a struct for dll settings instead of an array
Arthur Heymans
2017-05-21
nb/intel/x4x: Make raminit less verbose with CONFIG_DEBUG_RAM_SETUP
Arthur Heymans
2017-05-20
nb/intel/x4x/raminit: Remove very long delay
Arthur Heymans
2017-05-08
nb/x4x/raminit.c: Remove ME locking code
Arthur Heymans
2017-03-21
nb/x4x: Move checkreset before SPD reading
Arthur Heymans
2017-03-21
nb/intel/x4x: Fix issues found by checkpatch.pl
Arthur Heymans
2017-02-17
nb/intel/x4x: Implement resume from S3 suspend
Arthur Heymans
2017-02-17
nb/intel/x4x: Fix raminit on reset path
Arthur Heymans
2017-01-22
nb/x4x/raminit: Fix programming dram timings
Arthur Heymans
2016-11-21
nb/intel: Fix some spelling mistakes in comments and strings
Martin Roth
2016-11-08
nb/x4x/raminit.c: Improve crossclock table cosmetics
Arthur Heymans
2016-09-07
nb/intel/x4x: Increase MMIO PCI space to 2GiB
Damien Zammit
2016-08-31
northbridge/intel: Add required space before opening parenthesis '('
Elyes HAOUAS
2016-08-09
x4x: add non documented vram sizes
Arthur Heymans
2016-07-27
nb/intel/x4x: Fix CAS latency detection and max memory detection
Damien Zammit
2016-06-04
nb/intel/x4x: Fix unpopulated value
Damien Zammit
2016-01-29
nb/intel/x4x: Tidy up raminit and fix msbpos() function
Damien Zammit
2016-01-29
nb/intel/x4x: Fix memory hole with both channels populated
Damien Zammit
2016-01-13
northbridge/intel/x4x: clean up includes
Martin Roth
2015-12-30
northbridge/intel/x4x: Native raminit
Damien Zammit