index
:
coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
vimacs
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
northbridge
/
intel
/
x4x
/
rcven.c
Age
Commit message (
Expand
)
Author
2020-07-30
nb/intel/x4x/rcven.c: Rename memory barrier function
Angel Pons
2020-05-11
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-05-06
treewide: replace GPLv2 long form headers with SPDX header
Patrick Georgi
2020-05-06
treewide: Move "is part of the coreboot project" line in its own comment
Patrick Georgi
2020-03-17
src (minus soc and mainboard): Remove copyright notices
Patrick Georgi
2019-06-04
nb/intel/x4x/rcven.c: Remove variable set but not used
Elyes HAOUAS
2019-03-04
device/mmio.h: Add include file for MMIO ops
Kyösti Mälkki
2018-04-17
nb/intel/x4x/rcven.c: Change the verbosity of some messages
Arthur Heymans
2018-04-17
nb/intel/x4x: Add a convenient macro to loop over bytelanes
Arthur Heymans
2018-04-17
nb/intel/x4x: Clarify the raminit memory mapping
Arthur Heymans
2018-04-17
nb/intel/x4x: Use SPI flash to cache raminit results
Arthur Heymans
2017-12-12
nb/intel/x4x/rcven.c: Fix programming coarse offset
Arthur Heymans
2017-08-20
nb/intel/x4x/raminit: Rework receive enable calibration
Arthur Heymans