| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-05-20 | security/intel/txt: Add weak function to skip TXT lockdown | Arthur Heymans |
| 2020-11-04 | haswell: Add Intel TXT support in romstage | Angel Pons |
| 2020-07-31 | security/intel/txt: Add Intel TXT support | Philipp Deppenwiese |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |