coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-09-11	soc/amd/common/espi_util: clarify espi_open_io_window	Felix Held
2020-08-12	soc/amd/common/espi_util: rename espi_check_status	Felix Held
2020-08-11	soc/amd/common/espi_util: espi_send_command: improve error message	Felix Held
2020-08-11	soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug	Felix Held
2020-08-11	soc/amd/common/espi_util: simplify espi_std_io_decode function	Felix Held
2020-08-11	soc/amd/common/espi_util: make decode enable parameter uint32_t	Felix Held
2020-08-11	soc/amd/common/espi_util: make reg parameter unsigned	Felix Held
2020-07-16	soc/amd/common: Don't get eSPI address from PCI if not on x86	Martin Roth
2020-06-02	src: Remove redundant includes	Elyes HAOUAS
2020-05-13	soc/amd/common/block: Add support for configuring eSPI connection to slave	Furquan Shaikh
2020-05-13	Remove new additions of "this file is part of" lines	Furquan Shaikh
2020-05-12	soc/amd/common/block/lpc: Provide an option to use static eSPI BAR	Furquan Shaikh
2020-05-12	soc/amd/common/block/lpc: Add helpers for managing eSPI decode	Furquan Shaikh