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Some coreboot project code with my work
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romstage.c
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Author
2020-10-05
soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()
Nick Vaccaro
2020-10-05
mb, soc: change mainboard_get_dram_part_num() prototype
Nick Vaccaro
2020-05-11
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-04-06
soc/intel/cannonlake: Use SPDX for GPL-2.0-only files
Angel Pons
2020-03-18
soc: Remove copyright notices
Patrick Georgi
2019-12-26
soc/intel/cannonlake: Refactor pch_early_init() code
Usha P
2019-09-29
soc/intel: Rename <intelblocks/chip.h>
Kyösti Mälkki
2019-08-28
soc/intel: Move fill_postcar_frame to memmap.c
Kyösti Mälkki
2019-08-26
intel/car: Use common TS_START_ROMSTAGE
Kyösti Mälkki
2019-08-26
soc/intel: Use common romstage code
Kyösti Mälkki
2019-08-22
arch/x86: Add <arch/romstage.h>
Kyösti Mälkki
2019-07-04
arch/x86: Adjust size of postcar stack
Kyösti Mälkki
2019-06-21
soc/intel: Provide SPD manufacturer ID and module type to SMBIOS
Duncan Laurie
2019-06-06
src/soc/intel/common/smbios: Add addtional infos to dimm_info
Christian Walter
2019-05-18
soc/intel: Fill DIMM serial number from SPD
Duncan Laurie
2019-04-26
soc/{amd,intel}/chip: Use local include for chip.h
Elyes HAOUAS
2019-04-23
src: include <assert.h> when appropriate
Elyes HAOUAS
2019-03-13
soc/intel/cannonlake: Allow mainboard to override DRAM part number
Furquan Shaikh
2019-03-04
arch/io.h: Drop unnecessary include
Kyösti Mälkki
2019-02-18
soc/intel: Add mem_rank info in SMBIOS
Francois Toguo
2019-02-13
soc/intel/cannonlake: Don't use CAR_GLOBAL
Arthur Heymans
2019-01-08
soc/intel/cannonlake: Fix chipset_power_state structure
Duncan Laurie
2018-10-08
Move compiler.h to commonlib
Nico Huber
2018-10-04
soc/intel/cannonlake: Move the FSP related callbacks to separate files
Rizwan Qureshi
2018-09-28
soc/intel/cannonlake: Move SkipMpInit config to FSPM
Lijian Zhao
2018-06-04
soc/{amd,intel}: Use postcar_frame_add_romcache()
Nico Huber
2018-05-31
soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)
Nico Huber
2018-04-24
compiler.h: add __weak macro
Aaron Durbin
2018-04-19
soc/intel/cannonlake: Set DISB after Dram init
Lijian Zhao
2018-04-05
soc/intel/cannonlake: Add VT-d and VMX programming
Lijian Zhao
2018-02-14
intel/fsp: Update cannonlake fsp header
Lijian Zhao
2018-02-08
soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17
Subrata Banik
2018-01-25
soc/intel/cannonlake: enable pch link in bootblock
Caveh Jalali
2018-01-16
soc/intel/cannonlake: Program DMI PCR settings
Lijian Zhao
2017-12-20
soc/intel/cannonlake: Tell FSPM UART port number
Lijian Zhao
2017-10-19
soc/intel/cannonlake: Fix HECI error on reset
Lijian Zhao
2017-10-18
soc/intel/cannonlake: Set platform Debug Probe Type
Lijian Zhao
2017-10-03
soc/intel/cannonlake: Disable CPU ratio override
Lijian Zhao
2017-09-05
soc/intel/cannonlake: Set IGD stolen memory size to 64MB
Subrata Banik
2017-09-01
soc/intel/cannonlake: Define Max PCIE Root Ports
Pratik Prajapati
2017-08-30
soc/intel/cannonlake: Add PrmrrSize and C6DRAM config
Subrata Banik
2017-08-25
soc/intel/cannonlake: Init UPD params based on config
Pratik Prajapati
2017-08-21
soc/intel/cannonlake: Enable common PMC code for CNL
Lijian Zhao
2017-08-15
soc/intel/cannonlake: Add postcar stage support
Lijian Zhao
2017-07-24
Update files with no newline at the end
Martin Roth
2017-07-21
Revert "soc/intel/cannonlake: Add postcar stage support"
Martin Roth
2017-07-21
soc/intel/cannonlake: Add postcar stage support
Lijian Zhao
2017-07-19
soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit
Lijian Zhao