index
:
coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
vimacs
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
soc
/
intel
/
skylake
/
acpi
/
xhci.asl
Age
Commit message (
Expand
)
Author
2020-07-01
soc/intel/skylake: Update ASL syntax in xhci.asl
Edward O'Callaghan
2020-05-11
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-04-06
soc/intel/skylake: Use SPDX for GPL-2.0-only files
Angel Pons
2020-03-18
soc: Remove copyright notices
Patrick Georgi
2019-06-08
src/soc/intel/skylake/acpi: Remove Return for PS0/3
Christian Walter
2018-10-08
src: Use tabs for indentation
Elyes HAOUAS
2018-02-28
skylake: Fix unwanted disablement of ACPI UPWE
Kane Chen
2017-06-09
soc/skylake: add ACPI method to generate USB port info
Matt DeVillier
2017-04-07
soc/intel/skylake: Enable XHCI clock gate control in ACPI
Naresh G Solanki
2016-10-26
intel/skylake: Add support to enable wake-on-usb attach/detach
Furquan Shaikh
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-14
skylake: ACPI: Fix compiler warnings with iasl-20150717
Duncan Laurie
2015-09-08
skylake: ACPI: Clean up and fix XHCI ACPI Device
Duncan Laurie
2015-07-16
soc/intel: Add Skylake SOC support
Lee Leahy
2015-07-16
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC
Lee Leahy