coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2021-02-07	acpi: Fix BERT size_t printf format error	Benjamin Doron
2021-02-07	src: Remove redundant include <rules.h>	Elyes HAOUAS
2021-02-07	soc/intel/alderlake: Increase VBT size to 9 KiB	Maulik V Vaghela
2021-02-07	soc/amd/stoneyridge: remove STONEYRIDGE_ACPI_IO_BASE Kconfig option	Felix Held
2021-02-07	soc/amd/stoneyridge: remove STONEYRIDGE_ prefix of ACPI_IO_BASE define	Felix Held
2021-02-07	soc/intel/broadwell: Use common {DMI,EP,MCH}BAR accessors	Angel Pons
2021-02-07	soc/amd/cezanne/romstage: Store early dram region	Raul E Rangel
2021-02-07	soc/amd/picasso: Move memmap_early_dram to common blocks	Raul E Rangel
2021-02-07	soc/amd/cezanne/Makefile.inc: Fix indentation	Raul E Rangel
2021-02-07	soc/amd/cezanne/pcie_gpp: scan internal PCI buses	Felix Held
2021-02-07	soc/amd/cezanne/chip: add PCI bus scanning	Felix Held
2021-02-07	soc/intel/broadwell: Convert to ASL 2.0 syntax	Elyes HAOUAS
2021-02-06	drivers/intel/fsp2_0: Add support for MP services2 PPI	Aamir Bohra
2021-02-06	intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI	Furquan Shaikh
2021-02-06	intel: Drop FSP_PEIM_TO_PEIM_INTERFACE	Furquan Shaikh
2021-02-06	soc/intel/broadwell: Conditionally skip PRE_GRAPHICS_DELAY	Kyösti Mälkki
2021-02-06	soc/amd/stoneyridge: Create chipset_power_state in romstage	Kyösti Mälkki
2021-02-06	sb,soc/intel: Add wake source fields in GNVS	Kyösti Mälkki
2021-02-05	soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust	Chris Wang
2021-02-05	soc/amd/cezanne/iomap: move MMIO range comment above MMIO ranges	Felix Held
2021-02-05	soc/amd/cezanne/fch: add ACPI I/O port setup	Felix Held
2021-02-05	soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option	Felix Held
2021-02-05	soc/intel/broadwell: Convert some CONFIG(CHROMEOS) preprocessor	Kyösti Mälkki
2021-02-05	soc/amd/cezanne: populate some FSP-M UPDs	Felix Held
2021-02-05	soc/amd/common: Refactor single GPIO programming	Kyösti Mälkki
2021-02-05	soc/amd/common: Separate single GPIO programming	Kyösti Mälkki
2021-02-05	soc/mediatek/mt8192: Use LZ4 compression for MCUs	Yu-Ping Wu
2021-02-05	soc/intel/xeon_sp/cpx: Override SMBIOS type 4 max speed	Tim Chu
2021-02-05	soc/intel/skylake/acpi/irqlinks.asl: Fix typo in comment	Elyes HAOUAS
2021-02-05	soc/intel/alderlake: Refactor PCIE port config	Eric Lai
2021-02-05	soc/intel/broadwell/pch/lpc.c: Program GEN_PMCON_3 in one write	Angel Pons
2021-02-04	soc/amd/common/block/acpi/pm_state: add missing include	Felix Held
2021-02-04	soc/amd/picasso/fch: add missing iomap.h include	Felix Held
2021-02-04	drivers/intel/fsp2_0: Fix running on x86_64	Patrick Rudolph
2021-02-04	acpi: Add support for reporting CrashLog in BERT table	Francois Toguo
2021-02-04	src: Remove useless comments in "includes" lines	Elyes HAOUAS
2021-02-04	soc/amd/picasso: Fix copy-paste error in macro definitions	Angel Pons
2021-02-04	soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0	John Zhao
2021-02-04	src: Remove unused <bootstate.h>	Elyes HAOUAS
2021-02-04	src: Remove unused <cbfs.h>	Elyes HAOUAS
2021-02-04	soc/qualcomm/sc7180/aop_load_reset.c: Add missing <program_loading.h>	Elyes HAOUAS
2021-02-04	soc/mediatek/mt8192/spm.c: Add missing <string.h>	Elyes HAOUAS
2021-02-04	soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers	Felix Held
2021-02-04	amd/common/block/acpi/pm_state: fix comparison in get_index_bit	Felix Held
2021-02-03	soc/intel/tgl: Add configurable value for ConfigTdpLevel	Derek Huang
2021-02-03	soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports	Felix Held
2021-02-03	soc/amd/cezanne: remove UART2/3 AOAC device offsets	Felix Held
2021-02-03	soc/amd/picasso: clean up and re-sort UPD table	Chris Wang
2021-02-03	amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73)	Zheng Bao
2021-02-03	pci_ids/intel: Add missing CFL-S GT1 IGD IDs	Nico Huber