coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2021-01-24	soc/intel/quark/gpio_i2c.c: Use __func__	Elyes HAOUAS
2021-01-24	soc/intel/denverton_ns/pmc.c: Use __func__	Elyes HAOUAS
2021-01-24	soc/intel/denverton_ns/npk.c: Use __func__	Elyes HAOUAS
2021-01-24	soc/intel/denverton_ns/lpc.c: Use __func__	Elyes HAOUAS
2021-01-24	soc/samsung/exynos5250/dp-reg.c: Use __func__	Elyes HAOUAS
2021-01-24	soc/amd/cezanne/Kconfig: select missing SSE2 option	Felix Held
2021-01-24	soc/amd/cezanne/Kconfig: select X86_AMD_FIXED_MTRRS	Felix Held
2021-01-24	soc/amd/cezanne: add basic romstage	Felix Held
2021-01-24	soc,vendorcode/amd/cezanne: add basic FSP integration	Felix Held
2021-01-24	soc/amd/picasso: Remove some empty strings	Zheng Bao
2021-01-24	soc/amd/cezanne: Add PSP integration for cezanne	Zheng Bao
2021-01-24	soc/intel/xeon_sp/cpx: Account for 'rc' heap manager	Arthur Heymans
2021-01-24	soc/intel/lpc_lib: drop dead code	Michael Niewöhner
2021-01-24	soc/intel/icl: drop wrong, unused code	Michael Niewöhner
2021-01-24	soc/intel/cnl: use Kconfig to determine PCH type	Michael Niewöhner
2021-01-24	soc/intel/broadwell: Align raminit with Haswell	Angel Pons
2021-01-24	soc/intel/broadwell: Drop `struct romstage_params`	Angel Pons
2021-01-24	broadwell: Flatten `mainboard_pre_raminit`	Angel Pons
2021-01-24	broadwell: Clean up `mainboard_post_raminit`	Angel Pons
2021-01-24	soc/intel/broadwell/chip.h: Drop unused fields	Angel Pons
2021-01-24	soc/intel/broadwell: Select CPU_INTEL_HASWELL	Angel Pons
2021-01-24	soc/intel/broadwell: Move romstage.c to Haswell	Angel Pons
2021-01-24	soc/intel/broadwell: Drop now-unused CPU code	Angel Pons
2021-01-24	soc/intel/broadwell: Use Haswell CPU headers	Angel Pons
2021-01-24	soc/intel/broadwell: Allow to use Haswell CPU code instead	Angel Pons
2021-01-24	soc/intel/broadwell: Select INTEL_LYNXPOINT_LP	Angel Pons
2021-01-23	soc/intel/baytrail,broadwell: Use bootstate for save_wake_source()	Kyösti Mälkki
2021-01-23	ACPI: Add helpers for CBMEM_ID_POWER_STATE	Kyösti Mälkki
2021-01-23	soc/amd: Rename chipset_state to chipset_power_state	Kyösti Mälkki
2021-01-23	intel/baytrail,braswell,broadwell: Add const qualifier for power_state	Kyösti Mälkki
2021-01-23	ELOG: Add const qualifier for chipset_power_state	Kyösti Mälkki
2021-01-23	soc/amd/picasso/pcie_gpp: Remove duplication in pirq_data declaration	Raul E Rangel
2021-01-23	soc/amd/picasso/pci_gpp: Replace the swizzle string with a u8 array	Raul E Rangel
2021-01-23	soc/amd/picasso/pcie_gpp: Add clarifying comment	Raul E Rangel
2021-01-23	soc/amd/picasso/acpi: Remove dummy AOAC parent device	Raul E Rangel
2021-01-23	soc/intel/cometlake: Add ucode for CML-H	Tim Crawford
2021-01-23	soc/intel/apl: drop LPC pad configuration code	Michael Niewöhner
2021-01-22	soc/amd/cezanne: add pci_devs.h	Felix Held
2021-01-22	soc/intel/alderlake: Adding Kconfig for ADL_M PCH	Varshit Pandya
2021-01-22	soc/intel/commmon: Include Alder Lake device IDs	Varshit Pandya
2021-01-22	soc/mediatek/mt8192: pmic: Set efuses manually	Hsin-Hsiung Wang
2021-01-22	soc/mediatek/mt8183: Fix pq module size config	Yu-Ping Wu
2021-01-22	soc/amd/common/block/smbus: always return SMBus MMIO in get_sm_mmio	Felix Held
2021-01-22	soc/intel/baytrail,broadwell: Refactor acpi_wake_source()	Kyösti Mälkki
2021-01-21	soc/amd/cezanne: include LAPIC code and set MAX_CPUS to 16	Felix Held
2021-01-21	soc/intel/quark: Add pwrs in <soc/nvs.h>	Kyösti Mälkki
2021-01-21	soc/intel/cannonlake: Allow RP#1 usage for ClkSrc	Jeremy Soller
2021-01-21	soc/intel/common/pcie_rp.h: Fix comment style	Furquan Shaikh
2021-01-21	soc/intel/alderlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGD	Subrata Banik
2021-01-21	soc/intel/common/graphics: Add new Kconfig SOC_INTEL_DISABLE_IGD	Subrata Banik